Node contact structures in semiconductor devices

1. An interconnection structure in a semiconductor device, comprising:

an insulating layer including a contact hole extending therethrough on an active region of a semiconductor substrate;

a conductive layer pattern on the insulating layer; and

a multi-layer plug vertically extending completely through the contact hole in the insulating layer to electrically connect the conductive layer pattern and the active region, the multi-layer plug comprising a semiconductor plug directly on the active region and extending through at least a portion of the insulating layer, and a metal plug directly on the semiconductor plug and the conductive layer pattern and extending through at least a portion of the insulating layer, wherein the metal plug is directly on the active region and at least one sidewall of the semiconductor plug, and wherein the multi-layer plug does not extend directly on the insulating layer outside the contact hole.

2. The interconnection structure of claim 1 , wherein the semiconductor plug and the active region comprise a same conductivity type, and wherein the active region and the conductive layer pattern comprise different conductivity types.

3. The interconnection structure of claim 2 , wherein the semiconductor plug and the active region comprise an n-type conductivity, and wherein at least a portion of the conductive layer pattern comprises a p-type conductivity.

4. The interconnection structure of claim 1 , wherein the semiconductor plug comprises an intrinsic semiconductor and/or a different conductivity type than the active region.

5. The interconnection structure of claim 4 , wherein the semiconductor plug comprises a p-type conductivity, and wherein the active region comprises an n-type conductivity.

6. The interconnection structure of claim 1 , wherein the semiconductor plug is directly on the conductive layer pattern.

7. The interconnection structure of claim 6 , wherein the semiconductor plug is directly on a bottom surface of the conductive layer pattern, and wherein the metal plug is directly on a sidewall of the semiconductor plug and an end portion of the conductive layer pattern.

8. The interconnection structure of claim 1 , wherein the metal plug passes through a portion of the conductive layer pattern, and the semiconductor plug extends between the metal plug and the active region.

9. The interconnection structure of claim 1 , wherein the conductive layer pattern is a first conductive layer pattern, and further comprising:

a second conductive layer pattern on the insulating layer adjacent the first conductive layer pattern and directly on the metal plug.

10. The interconnection structure of claim 1 , wherein the conductive layer pattern and the semiconductor plug comprise single crystalline silicon.

11. The interconnection structure of claim 1 , wherein the metal plug is a metal layer having ohmic contact with both an n-type semiconductor and a p-type semiconductor.

12. The interconnection structure of claim 1 , wherein the active region comprises a source/drain region of a bulk MOS transistor, and wherein the conductive layer pattern comprises a source/drain region of a thin-film transistor.

13. The interconnection structure of claim 1 , wherein the contact hole in the insulating layer is free of oblique sidewalls.

14. The interconnection structure of claim 13 , wherein the multi-layer plug is horizontally confined within a perimeter defined by the contact hole.

15. The interconnection structure of claim 1 , wherein the multi-layer plug is horizontally confined within a perimeter defined by the contact hole.

16. A static random-access memory (SRAM) device, comprising:

a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;

an insulating layer including a contact hole extending therethrough on the bulk MOS transistor, wherein the insulating layer covers the bulk MOS transistor;

a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor; and

a multi-layer plug vertically extending completely through the contact hole in the insulating layer to electrically connect the source/drain region of the thin-film transistor and the source/drain region of the bulk MOS transistor, the multi-layer plug comprising a semiconductor plug extending through at least a portion of the insulating layer and directly on the source/drain region of the bulk MOS transistor, and a metal plug extending through at least a portion of the insulating layer and directly on the source/drain region of the thin-film transistor and the semiconductor plug, wherein the multi-layer plug does not extend directly on the insulating layer outside the contact hole.

17. The device of claim 16 , wherein the semiconductor plug and the source/drain region of the bulk MOS transistor comprise a same conductivity type, and wherein the source/drain region of the bulk MOS transistor and the source/drain region of the thin-film transistor comprise different conductivity types.

18. The device of claim 17 , wherein the semiconductor plug and the source/drain region of the bulk MOS transistor comprise an n-type conductivity, and wherein the source drain region of the thin-film transistor comprises a p-type conductivity.

19. The device of claim 16 , wherein the metal plug is directly on the source/drain region of the bulk MOS transistor and at least one outer sidewall of the semiconductor plug.

20. The device of claim 19 , wherein the semiconductor plug comprises an intrinsic semiconductor and/or a different conductivity type than the source/drain region of the bulk MOS transistor.

21. The device of claim 20 , wherein the semiconductor plug comprises a p-type conductivity, and wherein the source/drain region of the bulk MOS transistor comprises an n-type conductivity.

22. The device of claim 19 , wherein the semiconductor plug is directly on the source/drain region of the thin-film transistor.

23. The device of claim 16 , wherein the bulk MOS transistor is an n-channel metal oxide semiconductor (NMOS) transistor, and the thin film transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

24. The device of claim 16 , wherein the thin-film transistor is a first thin-film transistor, and further comprising:

a second thin-film transistor on the insulating layer adjacent the first thin-film transistor,

wherein the metal plug is directly on a gate electrode of the second thin-film transistor.

25. The device of claim 24 , wherein the bulk MOS transistor is a first bulk MOS transistor, wherein the metal plug is a first metal plug, and further comprising:

a second bulk MOS transistor on the substrate adjacent the first bulk MOS transistor; and

a second metal plug extending through at least a portion of the insulating layer and directly on the gate electrode of the second thin-film transistor and a gate electrode of the second bulk MOS transistor.

26. The device of claim 25 , wherein the gate electrode of the second bulk MOS transistor is an n-type polysilicon pattern, and wherein the gate electrode of the second thin-film transistor is a p-type polysilicon pattern.

27. The device of claim 24 , wherein the bulk MOS transistor is a driver transistor, wherein the first thin-film transistor is a load transistor, and wherein the second thin-film transistor is a transfer transistor for the static random-access memory device.

28. The device of claim 27 , wherein a word line is connected to the gate electrode of the second thin-film transistor.

29. The device of claim 27 , wherein a bit line is connected to a source/drain region of the second thin-film transistor.

30. The device of claim 16 , wherein the insulating layer on the bulk MOS transistor is a first insulating layer, and further comprising:

a second insulating layer on the thin-film transistor,

wherein the metal plug extends through the second insulating layer.

31. The device of claim 16 , wherein the thin-film transistor includes a body portion having a single crystalline silicon structure.

32. The device of claim 31 , wherein the body portion of the thin-film transistor is formed by a solid phase epitaxial process and has a same crystalline structure as the semiconductor plug.

33. The device of claim 16 , wherein the metal plug comprises a tungsten plug.

34. The device of claim 16 , wherein the metal plug comprises a tungsten plug and barrier metal layer surrounding the tungsten plug.

35. The interconnection structure of claim 16 , wherein the contact hole in the insulating layer is free of oblique sidewalls.

36. The interconnection structure of claim 35 , wherein the multi-layer plug is horizontally confined within a perimeter defined by the contact hole.

37. The interconnection structure of claim 16 , wherein the multi-layer plug is horizontally confined within a perimeter defined by the contact hole.

38. A semiconductor device comprising an interconnection structure, the interconnection structure comprising:

a first transistor on a substrate having a first conductive region;

an insulating layer on the first conductive region and covering the first transistor, wherein the insulating layer includes a contact hole extending therethough;

a second transistor on the insulating layer having a second conductive region; and

a multi-plug vertically extending through the contact hole in the insulating layer to electrically connect the first conductive region and the second conductive region, the multi-plug comprising a silicon plug connected to the first conductive region through at least a portion of the insulating layer, and a metal plug connected to the silicon plug and the second conductive region through at least a portion of the insulating layer, wherein the multi-plug does not extend directly on the insulating layer outside the contact hole.

39. The semiconductor device of claim 38 , wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

40. The semiconductor device of claim 38 , wherein the first and the second conductive regions are a source/drain region of the first and second transistors respectively.

41. The interconnection structure of claim 38 , wherein the multi-plug is horizontally confined within a perimeter defined by the contact hole.

42. The interconnection structure of claim 38 , wherein the contact hole in the insulating layer is free of oblique sidewalls.

43. A semiconductor device comprising an interconnection structure, the interconnection structure comprising:

a first transistor on a substrate having a first conductive region;

an insulating layer on the first conductive region and covering the first transistor, wherein the insulating layer includes a contact hole extending therethough;

a second transistor on the insulating layer having a second conductive region; and

a multi-plug vertically extending through the contact hole in the insulating layer to electrically connect the first conductive region and the second conductive region, the multi-plug comprising a first plug connected to the first conductive region and the second conductive region, and a second plug connected to the first conductive region and the second conductive region, wherein the first and the second plugs are directly connected to each other, and wherein the multi-plug does not extend directly on the insulating layer outside the contact hole.

44. The semiconductor device of claim 43 , wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

45. The semiconductor device of claim 43 , wherein the first and the second conductive regions are a source/drain region of the first and second transistors, respectively.

46. The semiconductor device of claim 43 , wherein the first plug comprises silicon and the second plug comprises metal.

47. The interconnection structure of claim 43 , wherein the multi-plug is horizontally confined within a perimeter defined by the contact hole.

48. The interconnection structure of claim 43 , wherein the contact hole in the insulating layer is free of oblique sidewalls.