IP Library Granted Patent US 7,329,931
Granted Patent B2
US 7,329,931 · App. 11/033,213 · Granted Feb 12, 2008

Receiver circuit using nanotube-based switches and transistors

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Quick Facts
Patent No.
US 7,329,931
App. No.
11/033,213
Granted
Feb 12, 2008
Kind
B2
Abstract

Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

Claims (11)

1. A receiver circuit, comprising:

a differential input having a first and second input link;

a differential output having a first and second output link;

first and second switching elements in electrical communication with the input links and the output links, each switching element having an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node; and

first and second MOS transistors, each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

2. The receiver circuit of claim 1 wherein the first and second MOS transistors are PFET transistors in electrical communication with Vdd voltage and wherein the output node of a first switching element is coupled to the drain of the first MOS transistor and a gate of the second MOS transistor, and wherein the output node of a second switching element is coupled to the drain of the second MOS transistor and a gate of the first MOS transistor.

3. The receiver circuit of claim 1 wherein the first and second switching elements retail channel formation non-volatilely.

4. The receiver circuit of claim 2 wherein the input node of each switching element is in electrical communication with ground.

5. The receiver circuit of claim 4 wherein the control structure of each switching element includes a set electrode and a release electrode, wherein the set electrode is activated to cause the nanotube channel element to electrically and mechanically contact the output node to form a channel, and wherein the release electrode is activated to cause the nanotube channel element to release electrical and mechanical contact with the output node to unform the channel.

6. The receiver circuit of claim 5 wherein a first link of the differential input is coupled to the set electrode of the first switching element and the release electrode of the second switching element, and wherein a second link of the differential input is coupled to the set electrode of the second switching element and the release electrode of the first switching element.

7. The receiver circuit of claim 6 wherein the output nodes of the first and second switching elements are coupled, respectively, to a first and second output link of the differential output.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056790/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →