Insulating substrate for IC packages having integral ESD protection
View Patent ↗An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed
1. An integrated circuit package assembly with integral electrostatic discharge (ESD) protection, the integrated circuit package assembly comprising:
an integrated circuit die;
circuit layer traces interconnected to the integrated circuit die;
an insulting base layer, wherein a portion of the circuit layer traces are disposed along a first side of the insulating base layer;
a conductive layer disposed on the second side of the insulating base layer; and
ESD paths extending from the first side of the insulating base layer to the second side of the insulating base layer, wherein at least some of the circuit layer traces are in electrical contact with at least one ESD path.
2. The integrated circuit package assembly of claim 1 wherein the ESD paths comprise a gas.
3. The integrated circuit package assembly of claim 2 wherein the gas comprises air.
4. The integrated circuit package assembly of claim 2 wherein each of the ESD paths are in physical contact with at least one of the circuit layer traces, and with the conductive layer.
5. The integrated circuit package assembly of claim 1 wherein the ESD paths comprise a voltage-switchable material.
6. The integrated circuit package assembly of claim 1 wherein the integrated circuit die is coupled to the first side of the insulating layer by a die adhesive.
7. The integrated circuit package assembly of claim 1 wherein the ESD paths are configured to prevent electrical current flow between the circuit layer traces and the conductive layer when a voltage potential between the circuit layer traces and the conductive layer is below a predetermined discharge voltage, and to permit an electrical discharge current when the voltage potential between the circuit layer traces and the conductive layer exceeds the predetermined discharge voltage.
8. The integrated circuit package assembly of claim 7 wherein the electric discharge current is a spark.
9. The integrated circuit package assembly of claim 7 wherein the predetermined threshold voltage is approximately 40 volts.
10. The integrated circuit package assembly of claim 1 wherein the thickness of the insulating base layer is approximately 25 μm.
11. The integrated circuit package assembly of claim 1 wherein the ESD path is a polymer.
12. The integrated circuit package assembly of claim 1 wherein the ESD path comprises a squeegeeable material.
13. The integrated circuit package assembly of claim 1 wherein the ESD path comprises a sputterable material.
14. The integrated circuit package assembly of claim 1 wherein the conductive layer comprises copper.
15. The integrated circuit package of claim 1 further comprising a next-level interconnect zone.
16. The integrated circuit package assembly of claim 15 wherein the next-level interconnect zone comprises:
a) a hole in the insulating base layer extending from the first side of the insulating base layer to the conductive layer; and
b) a solder ball partially disposed within the hole, and electrically coupled to the conductive layer.
17. An integrated circuit package assembly comprising:
a) an integrated circuit die having a plurality of terminals, the integrated circuit die coupled to a first side of an insulating layer;
b) a conductive layer coupled to a second side of an insulating layer;
c) a plurality of redistribution circuits disposed on the first side of the insulating layer, wherein at least some of the redistribution circuits have a narrow trace portion coupled to a respective terminal on the integrated circuit die; and
d) a plurality of ESD paths extending from the first side of the insulating layer to the conductive layer, wherein at least some of the redistribution circuits are in electrical contact with at least one ESD path.