Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features
View Patent ↗An integrated circuit chip having programmable functions and features in which one-time programmable (OTP) memories are used to implement a non-volatile memory function, and a method for providing the same. The OTP memories may be based on poly-fuses as well as gate-oxide fuses. Because OTP memories are small, less die area is utilized as compared to metal fuses. Addtionally, because OTP memories can be implemented as part of standard complementary metal oxide semiconductor (CMOS) processes, the method is less costly and complex than the use of electrically-erasable programmable read-only memories (E2PROMs).
1. A programmable integrated circuit chip, comprising:
a circuit block configured to perform a function; and
a one-time programmable (OTP) memory connected to the circuit block, the OTP memory being programmed after packaging of the circuit chip with a programmed state;
wherein the circuit block is responsive to the programmed state of the OTP memory to perform the function in one of a plurality of operating modes.
2. The programmable integrated circuit chip of claim 1 , wherein the circuit chip is manufactured using a complementary metal oxide semiconductor (CMOS) process.
3. The programmable integrated circuit chip of claim 1 , wherein the OTP memory comprises at least one OTP memory cell, the OTP memory cell including a non-volatile storage element and a fuse element.
4. The programmable integrated circuit chip of claim 3 , further comprising a redundant OTP memory cell corresponding to the at least one OTP memory cell, whereby the redundant OTP memory cell provides additional storage in the instance that the at least one OTP memory cell is non-functional or is sought to be reprogrammed.
5. The programmable integrated circuit chip of claim 3 , wherein the fuse element comprises a gate-oxide fuse element.
6. The programmable integrated circuit chip of claim 3 , wherein the fuse element comprises a poly-fuse element.
7. The programmable integrated circuit chip of claim 1 , further comprising:
an external pin coupled to the OTP memory, the external pin providing a means for writing to the OTP memory.
8. The programmable integrated circuit chip of claim 1 , wherein the circuit block comprises a reference voltage generator configured to generate a reference voltage and wherein the reference voltage generator is responsive to a programmed state of the OTP memory to alter the level of the reference voltage.
9. The programmable integrated circuit chip of claim 1 , wherein the circuit block comprises a power sequencer configured to generate a sequence of output voltages and wherein the power sequencer is responsive to a programmed state of the OTP memory to alter the sequence of output voltages.
10. The programmable integrated circuit chip of claim 1 , further comprising:
optimization logic coupled to the circuit block and the OTP memory, the optimization logic configured to determine an optimized operating parameter for the circuit block and to store state information relating to the optimized operating parameter in the OTP memory.
11. The programmable integrated circuit chip of claim 10 , wherein the optimized operating parameter is one or more of a voltage level, a frequency, a current, or a charge.
12. A programmable integrated circuit, comprising:
a one-time programmable (OTP) memory; and
optimization logic connected to the OTP memory, the optimization logic configured to determine an optimized operating parameter for a device external to the programmable integrated circuit and to store state information relating to the optimized operating parameter in the OTP memory for subsequent access by the external device.
13. The programmable integrated circuit chip of claim 12 , wherein the optimized operating parameter is one or more of a voltage level, a frequency, a current, or a charge.
14. A method for operating a programmable integrated circuit chip that includes a one-time programmable (OTP) memory, comprising:
programming the OTP memory after packaging of the circuit chip;
performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the OTP memory.
15. The method of claim 14 , wherein programming the OTP memory comprises programming an OTP memory cell, wherein the OTP memory cell comprises a fuse element and a storage element.
16. The method of claim 15 , wherein programming the OTP memory cell comprises blowing the fuse element within the OTP memory cell.
17. The method of claim 16 , wherein blowing the fuse element within the OTP memory cell comprises blowing a gate-oxide fuse element within the OTP memory cell.
18. The method of claim 16 , wherein blowing the fuse element within the OTP memory cell comprises blowing a poly-fuse element within the OTP memory cell.
19. The method of claim 14 , wherein programming the OTP memory comprises performing a memory write operation via an external pin of the programmable integrated circuit chip.
20. The method of claim 14 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the OTP memory comprises generating a reference voltage wherein the level of the reference voltage is determined based on the programmed state of the OTP memory.
21. The method of claim 14 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the OTP memory comprises generating a sequence of output voltages wherein the sequence is determined based on the programmed state of the OTP memory.
22. The method of claim 14 , wherein performing a function within the programmable integrated circuit chip in one of a plurality of operating modes in response to the programmed state of the OTP memory comprises generating one of a frequency, a current, or a charge based on the programmed state of the OTP memory.
23. The method of claim 14 , further comprising:
determining an optimized operating parameter for performing the function within the programmable integrated circuit chip;
wherein programming the OTP memory after packaging of the circuit chip comprises storing state information relating to the optimized parameter in the OTP memory.
24. The method of claim 23 , wherein determining an optimized operating parameter comprises determining one or more of a voltage level, a frequency, a current, or a charge.
25. A method for operating a programmable integrated circuit chip that includes a one-time programmable (OTP) memory, comprising:
determining an optimized operating parameter for the performance of a function by a device external to the programmable integrated circuit chip;
storing state information relating to the optimized operating parameter in the OTP memory for subsequent access by the external device.
26. The method of claim 25 , wherein determining an optimized operating parameter comprises determining one or more of a voltage level, a frequency, a current, or a charge.