Semiconductor circuit for DC-DC converter
View Patent ↗In a semiconductor integrated circuit for a DC—DC converter, an nMOS-type transistor Qn of a CMOS inverter 1 c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11 . Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q 1 and an L-pnp-type transistor Q 2 constituting a feedback control system 9 through the n-type well region 11 . Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.
1. A semiconductor integrated circuit for a DC—DC converter comprising:
a CMOS inverter configured to switch a DC input voltage, for providing an output to an inductive load therein, and
a feedback control system for generating a control voltage responsive to an output voltage to be fed back to said CMOS inverter,
repeating the switching so as to finally obtain a desired DC output voltage,
said semiconductor integrated circuit comprising transistors constituting said CMOS inverter and other transistors constituting said feedback control system, said transistors and said other transistors being integrated on a same semiconductor substrate therein, wherein
an nMOS-type transistor which is one of said transistors constituting said CMOS inverter is formed on said semiconductor substrate through a semiconductor region electrically insulated from said other transistors constituting said feedback control system.
2. The semiconductor integrated circuit for the DC—DC converter according to claim 1 , wherein said semiconductor region is an n-type well region.
3. The semiconductor integrated circuit for the DC—DC converter according to claim 2 , wherein said n-type well region is formed by same process steps as a region constituting at least one of said other transistors.
4. The semiconductor integrated circuit for the DC—DC converter according to claim 2 , wherein said n-type well region is connected to a stable potential.
5. The semiconductor integrated circuit according to claim 4 , wherein the stable potential is a power supply potential or a ground potential.
6. The semiconductor integrated circuit for the DC—DC converter according to claim 1 , wherein a timing adjustment circuit for constituting a final stage of said feedback control system and preventing a through current from flowing through said CMOS inverter is connected to said CMOS inverter.
7. The semiconductor integrated circuit for the DC—DC converter according to claim 6 , wherein said timing adjustment circuit sets a time for simultaneously switching off said nMOS-type transistor and a pMOS-type transistor constituting said CMOS inverter.
8. The semiconductor integrated circuit for the DC—DC converter according to claim 1 , wherein said DC—DC converter comprises a step-down type converter.