Integrated circuit including an overvoltage protection circuit
View Patent ↗The power IC includes an output transistor M 0 which controls a current flowing into an L load, a dynamic clamp circuit which clamps an overvoltage, and a clamp control circuit which controls the operation of the dynamic clamp circuit. The clamp control circuit activates the dynamic clamp circuit, which is normally inactive, upon detection of a back EMF by the L load.
1. An integrated circuit, comprising:
an output transistor adapted to be connected between a power supply and an inductive load for controlling a current flowing into the inductive load;
a clamp circuit for clamping an overvoltage applied to the output transistor; and
a clamp control circuit responsive to detection of a back electromotive force from the inductive load, for activating the clamp circuit,
wherein the clamp control circuit comprises a gate detection transistor for detecting a change in the gate voltage of the output transistor and a clamp switch transistor for turning on or off the clamp circuit according to a state of the gate detection transistor.
2. The integrated circuit of claim 1 , wherein the output transistor comprises an N-channel metal-oxide-semiconductor (MOS) transistor.
3. The integrated circuit of claim 1 , wherein the output transistor comprises a vertical metal-oxide-semiconductor (MOS) transistor.
4. The integrated circuit of claim 1 , wherein the clamp control circuit detects the back electromotive force by monitoring a gate voltage of the output transistor.
5. The integrated circuit of claim 4 , wherein the clamp control circuit is responsive to a change in the gate voltage to activate the clamp circuit, and is responsive to a lack of change in the gate voltage to deactivate the clamp circuit.
6. The integrated circuit of claim 4 , wherein the gate voltage comprises a potential difference between a gate of the output transistor and an output terminal to which the inductive load is connected.
7. The integrated circuit of claim 6 , wherein the clamp control circuit is responsive to a change in the gate voltage to activate the clamp circuit, and is responsive to a lack of change in the gate voltage to deactivate the clamp circuit.
8. The integrated circuit of claim 6 , wherein the clamp control circuit comprises:
a gate detection transistor for detecting a change in the gate voltage of the output transistor; and
a clamp switch transistor for turning on or off the clamp circuit according to a state of the gate detection transistor.
9. The integrated circuit of claim 1 , wherein the output transistor comprises a high side switch.
10. The integrated circuit of claim 2 , wherein the output transistor comprises a vertical metal-oxide-semiconductor (MOS) transistor.
11. An integrated circuit, comprising:
an output transistor having a control terminal and having a current path connected between a power supply terminal and a load terminal;
a clamp circuit for clamping an overvoltage applied to the output transistor; and
a clamp control circuit responsive to a voltage difference between the current control terminal of the output transistor and the load connecting terminal, for controlling operation of the clamp circuit,
wherein the clamp circuit is activated in a period that is variable corresponding to the voltage difference.
12. An integrated circuit, comprising:
an output transistor having a drain, adapted to be connected to a power supply, and a source, adapted to be connected to an inductive load;
a first transistor and a dynamic clamp circuit connected to a gate of the output transistor and adapted to be connected in series between the power supply and the gate of the output transistor; and
a second transistor connected to the inductive load and adapted to be connected to the power supply, for turning on or off the first transistor according to a change in a gate voltage of the output transistor.
13. The integrated circuit of claim 12 , further comprising a resistor, and wherein:
the second transistor has a gate connected to the gate of the output transistor, a drain adapted to be connected to the power supply via the resistor, and a source adapted to be connected to the inductive load, and
the first transistor has a gate connected to the drain of the second transistor, a source adapted to be connected to the power supply, and a drain connected to the dynamic clamp circuit.
14. The integrated circuit of claim 12 , wherein the second transistor is responsive to a decrease of a preselected amount in the gate voltage of the output transistor to turn on the first transistor.
15. The integrated circuit of claim 14 , further comprising a resistor, and wherein the gate of the second transistor is connected to the gate of the output transistor via the resistor.
16. The integrated circuit of claim 12 , wherein the second transistor is responsive to an increase of a preselected amount in the gate voltage of the output transistor to turn on the first transistor.
17. The integrated circuit of claim 16 , further comprising a diode, and wherein the gate of the second transistor is connected to the gate of the output transistor via the diode.
18. The integrated circuit of claim 12 , wherein the dynamic clamp circuit comprises:
a clamp diode for clamping an overvoltage; and
a backflow prevention diode connected in series with the clamp diode for preventing current backflow.
19. The integrated circuit of claim 18 , wherein the first transistor is connected between the clamp diode and the backflow prevention diode.