Method to improve high frequency divider bandwidth coverage
View Patent ↗A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.
1. A divider for a local oscillator (LO) generator system, the divider having at least one divider unit, each divider unit comprising:
a frequency divider unit adapted for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency;
a resistor bank coupled between a voltage source and the frequency divider unit; and
a current stirring unit adapted for supplying current to the frequency divider unit,
wherein a resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are adapted to be varied depending on the input frequency.
2. The divider of claim 1 , wherein the at least one divider unit includes two divider units arranged in series, such that a first one of the divider units receives a signal having a first frequency as the input signal and outputs a signal having a second frequency, which is approximately one half of the first frequency, as the output signal, and a second one of the divider units receives the signal having the second frequency as the input signal, and outputs a signal having a third frequency, which is approximately one half of the second frequency, as the output signal.
3. The divider of claim 1 , wherein the frequency divider unit comprises:
an input device for receiving the input signal having the input frequency; and
a latch coupled between the resistor bank and the input device for outputting the output signal having the output frequency.
4. The divider of claim 1 , wherein the resistance of the resistor bank is adapted decrease as the input frequency increases, and is adapted to increase as the input frequency decreases.
5. The divider of claim 4 , wherein the magnitude of the current supplied by the current stirring unit increases as the input frequency increases, and decreases as the input frequency decreases.
6. The divider of claim 1 , wherein a control signal comprising a plurality of binary bits are provided to the resistor bank and the current stirring unit to control the resistance of the resistor bank and the magnitude of the current supplied by the current stirring unit.
7. The divider of claim 6 , wherein each divider unit further comprises an inverter unit for inverting the binary bits prior to providing them to the current stirring unit.
8. The divider of claim 1 , wherein the frequency divider unit is a differential divider for receiving the input signal comprising a differential pair of input signals, and for outputting the output signal comprising a differential pair of output signals.
9. The divider of claim 8 , wherein the frequency divider unit further outputs another differential pair of output signals that are offset in phase from the differential pair of output signals by approximately 90 degrees.
10. A local oscillator (LO) generator system comprising:
a voltage controlled oscillator (VCO) for generating an output corresponding to a control voltage applied thereto;
a VCO buffer for receiving the output generated by the VCO and for providing a buffered output; and at least one divider, each divider having at least one divider unit, each divider unit comprising:
a frequency divider unit adapted for receiving the buffered output as an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency;
a resistor bank coupled between a voltage source and the frequency divider unit; and
a current stirring unit adapted for supplying current to the frequency divider unit,
wherein a resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are adapted to vary depending on the input frequency.
11. The LO generator system of claim 10 , wherein the at least one divider unit includes two divider units arranged in series, such that a first one of the divider units receives a signal having a first frequency as the input signal and outputs a signal having a second frequency, which is approximately one half of the first frequency, as the output signal, and a second one of the divider units receives the signal having the second frequency as the input signal, and outputs a signal having a third frequency, which is approximately one half of the second frequency, as the output signal.
12. The LO generator system of claim 10 , wherein the frequency divider unit comprises:
an input device for receiving the input signal having the input frequency; and
a latch coupled between the resistor bank and the input device for outputting the output signal having the output frequency.
13. The LO generator system of claim 10 , wherein the resistance of the resistor bank is adapted to decrease as the input frequency increases, and is adapted to increase as the input frequency decreases.
14. The LO generator system of claim 13 , wherein the magnitude of the current supplied by the current stirring unit increases as the input frequency increases, and decreases as the input frequency decreases.
15. The LO generator system of claim 10 , wherein a control signal comprising a plurality of binary bits are provided to the resistor bank and the current stirring unit to control the resistance of the resistor bank and the magnitude of the current supplied by the current stirring unit.
16. The LO generator system of claim 15 , wherein each divider unit further comprises an inverter unit for inverting the binary bits prior to providing them to the current stirring unit.
17. The LO generator system of claim 10 , wherein the frequency divider unit is a differential divider for receiving the input signal comprising a differential pair of input signals, and for outputting the output signal comprising a differential pair of output signals.
18. The LO generator system of claim 17 , wherein the frequency divider unit further outputs another differential pair of output signals that are offset in phase from the differential pair of output signals by approximately 90 degrees.
19. In a divider of a local oscillator (LO) generator system, the divider having at least one divider unit, each divider unit comprising a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency, a resistor bank coupled to the frequency divider unit, a current stirring unit for supplying current to the frequency divider unit, a method of improving bandwidth coverage, comprising:
adjusting a resistance of the resistor bank based on the input frequency; and
adjusting a magnitude of the current supplied by the current stirring unit based on the input frequency.
20. The method of claim 19 , wherein adjusting the resistance of the resistor bank comprises decreasing the resistance of the resistor bank when the input frequency increases, and increasing the resistance of the resistor bank when the input frequency decreases.
21. The method of claim 20 , wherein adjusting the magnitude of the current supplied by the current stirring unit comprises increasing the magnitude of the current when the input frequency increases, and decreasing the magnitude of the current when the input frequency decreases.
22. The method of claim 19 , wherein adjusting resistance of the resistor bank and adjusting a magnitude of the current are performed by providing a control signal comprising a plurality of binary bits, which change states in accordance with the input frequency.