Sense amplifier with adaptive reference generation

1. An apparatus for use in a memory system that includes a sense amplifier and a memory cell, comprising:

a bit line;

a transfer gate;

a reference voltage generator; and

a control circuit operative during a first mode of operation to precharge the bit line to generate a bit line precharge voltage and to cause the transfer gate to sample and store the precharge voltage and operative during a second mode of operation to cause the transfer gate to isolate the bit line from the sampled and stored precharge voltage, to cause the reference voltage generator to generate the reference voltage in response to the sampled and stored precharge voltage and to operatively couple the bit line and the reference voltage to the sense amplifier.

2. The apparatus according to claim 1 , comprising:

a supply voltage,

wherein the reference voltage generator comprises a first capacitor and a second capacitor, and

wherein the reference voltage comprises the sampled and stored precharge voltage modified by a fraction of the supply voltage determined at least in part by the relative values of the first capacitor and the second capacitor.

3. The apparatus according to claim 2 , wherein the control circuit is operative to operatively couple at least one of the first and second capacitors to the reference voltage generator after the bit line has been isolated from the sampled and stored precharge voltage.

4. The apparatus according to claim 1 , wherein the sense amplifier comprises a differential sense amplifier.

5. The apparatus according to claim 1 , wherein the control circuit comprises:

a precharge transistor arranged to precharge the bit line during the first mode of operation;

a first switch transistor arranged to operatively couple the sense amplifier to the bit line during the second mode of operation;

a second switch transistor arranged to operatively couple the reference voltage to the sense amplifier during the second mode of operation; and

a third switch transistor arranged to isolate the sense amplifier from the supply voltage during at least the second mode of operation.

6. A method of operating a memory system that includes a memory cell and a sense amplifier in which the sense amplifier receives a voltage based on a charge stored in the memory cell, the method comprising:

precharging a bit line to generate a bit line precharge voltage;

sampling and storing the bit line precharge voltage;

isolating the bit line horn the sampled and stored bit line precharge voltage; and

generating a reference voltage in response to the sampled and stored precharge voltage.

7. The method according to claim 6 , wherein generating the reference voltage comprises modifying the sampled and stored precharge voltage to a fraction of the supply voltage via capacitance dividing.

8. The method according to claim 6 , wherein generating the reference voltage occurs after isolating the bit line.

9. The method according claim 6 , wherein the sense amplifier comprises a differential sense amplifier.

10. The method according to claim 9 , comprising:

isolating the sense amplifier before energizing the sense amplifier.

11. The method according to claim 6 , wherein the method occurs in the order as set forth in claim 6 .

12. A circuit for use in a memory system that includes a sense amplifier and a memory cell, comprising:

means for receiving, by the sense amplifier, a voltage based on a charge stored in the memory cell;

means for precharging a bit line to generate a bit line precharge voltage;

means the sampling and storing the bit line precharged voltage;

means for isolating the bit line from the sampled and stored bit line precharge voltage; and

means for generating a reference voltage in response to the sampled and stored precharge voltage.