Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
View Patent ↗A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.
1. A method for making a semiconductor device comprising:
providing a substrate; and
forming at least one MOSFET adjacent the substrate by
forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,
each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
forming source, drain and gate regions defining a channel through at least a portion of the semiconductor cap layer.
2. The method of claim 1 wherein the channel lies entirely within the semiconductor cap layer.
3. The method of claim 1 wherein the semiconductor cap layer comprises the same semiconductor as each base semiconductor portion.
4. The method of claim 1 wherein the semiconductor cap layer comprises a different semiconductor than each base semiconductor portion.
5. The method of claim 1 wherein the semiconductor cap layer has a thickness of greater than about 10 Angstroms.
6. The method of claim 1 wherein each base semiconductor portion comprises silicon.
7. The method of claim 1 wherein each non-semiconductor monolayer comprises oxygen.
8. The method of claim 1 wherein each at least one non-semiconductor monolayer is a single monolayer thick.
9. The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
10. The method of claim 1 wherein the gate region comprises a gate electrode layer and a gate dielectric layer between the gate electrode layer and the semiconductor cap layer.
11. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
12. The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
13. The method of claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
14. The method of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
15. The method of claim 1 wherein the non-semiconductor is selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
16. The method of claim 1 further comprising implanting at least one type of conductivity dopant in the superlattice.
17. A method for making a semiconductor device comprising:
providing a substrate; and
forming at least one MOSFET adjacent the substrate by
forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,
each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
the semiconductor cap layer comprising the same semiconductor as each base semiconductor portion, and
forming source, drain and gate regions defining a channel lying entirely within the semiconductor cap layer.
18. The method of claim 17 wherein the semiconductor cap layer has a thickness of greater than about 10 Angstroms.
19. The method of claim 17 wherein each base semiconductor portion comprises silicon.
20. The method of claim 17 wherein each non-semiconductor monolayer comprises oxygen.
21. The method of claim 17 wherein each at least one non-semiconductor monolayer is a single monolayer thick.
22. The method of claim 17 wherein each base semiconductor portion is less than eight monolayers thick.
23. The method of claim 17 wherein the gate region comprises a gate electrode layer and a gate dielectric layer between the gate electrode layer and the semiconductor cap layer.
24. The method of claim 17 wherein all of the base semiconductor portions are a same number of monolayers thick.
25. The method of claim 17 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
26. The method of claim 17 wherein all of the base semiconductor portions are a different number of monolayers thick.
27. The method of claim 17 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
28. The method of claim 17 wherein the non-semiconductor is selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
29. A method for making a semiconductor device comprising:
providing a substrate; and
forming at least one MOSFET adjacent the substrate by
forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers,
each group of layers of the superlattice comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and
forming source, drain and gate regions defining a channel through at least a portion of the semiconductor cap layer.
30. The method of claim 29 wherein the channel lies entirely within the semiconductor cap layer.
31. The method of claim 29 wherein the semiconductor cap layer comprises the same semiconductor as each base silicon portion.
32. The method of claim 29 wherein the semiconductor cap layer comprises a different semiconductor than each base silicon portion.
33. The method of claim 29 wherein the semiconductor cap layer has a thickness of greater than about 10 Angstroms.
34. The method of claim 29 wherein each at least one oxygen monolayer is a single monolayer thick.
35. The method of claim 29 wherein each base silicon portion is less than eight monolayers thick.
36. The method of claim 29 wherein the gate region comprises a gate electrode layer and a gate dielectric layer between the gate electrode layer and the semiconductor cap layer.
37. The method of claim 29 wherein all of the base silicon portions are a same number of monolayers thick.
38. The method of claim 29 wherein at least some of the base silicon portions are a different number of monolayers thick.
39. The method of claim 29 wherein all of the base silicon portions are a different number of monolayers thick.