Patent Assignment
Reel/Frame 053681/0942
Release of Security Interest
Recorded: 2020-09-03
Pages: 15
Assignor
CLIFFORD, ROBERT
Executed: 2020-09-01
Assignee
ATOMERA INCORPORATED
750 UNIVERSITY AVE, SUITE 280, LOS GATOS, CALIFORNIA, 95032
Covered Properties
(58)
Wavelength Selective Filter
Patent:
6,141,361 →
Application:
08/817,876 →
Configurable Aperiodic Grating Device
Patent:
7,123,792 →
Application:
09/914,944 →
Farby-Perot Laser with Wavelength Control
Semiconductor Device Including Band-Engineered Superlattice
Method for Making Semiconductor Device Including Band-Engineered Superlattice
Semiconductor Device Including Mosfet Having Band-Engineered Superlattice
Optical Filter Device with Aperiodically Arranged Grating Elements
Method for Making Semiconductor Device Including Band-Engineered Superlattice
Method for Making Semiconductor Device Including Band-Engineered Superlattice
Patent:
6,878,576 →
Application:
10/716,991 →
Semiconductor Device Including Band-Engineered Superlattice
Method for Making Semiconductor Device Including Band-Engineered Superlattice
Semiconductor Device Including Band-Engineered Superlattice
Semiconductor Device Including Band-Engineered Superlattice
Integrated Circuit Comprising an Active Optical Device Having an Energy Band Engineered Superlattice
Electronic Device Comprising Active Optical Devices with an Energy Band Engineered Superlattice
Method for Making an Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice
Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice
Method for Making a Semiconductor Device Comprising a Superlattice Channel Vertically Stepped Above Source and Drain Regions
Semiconductor Device Comprising a Superlattice Channel Vertically Stepped Above Source and Drain Regions
Method for Making Semiconductor Device Comprising a Superlattice with Upper Portions Extending Above Adjacent Upper Portions of Source and Drain Regions
Semiconductor Device Comprising a Superlattice with Upper Portions Extending Above Adjacent Upper Portions of Source and Drain Regions
Semiconductor Device Including Band-Engineered Superlattice Having 3/1-5/1 Germanium Layer Structure
Method for Making a Semiconductor Device Including Band-Engineered Superlattice Having 3/1-5/1 Germanium Layer Structure
Semiconductor Device Including a Mosfet Having a Band-Engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
Method for Making a Semiconductor Device Including a Mosfet Having a Band-Engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
Semiconductor Device Including Mosfet Having Band-Engineered Superlattice
Method for Making a Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer with Doped Regions Defining a Semiconductor Junction
Semiconductor Device Including a Superlattice with Regions Defining a Semiconductor Junction
Semiconductor Device Including a Superlattice and Adjacent Semiconductor Layer with Doped Regions Defining a Semiconductor Junction
Method for Making a Semiconductor Device Including a Superlattice with Regions Defining a Semiconductor Junction
Method for Making a Semiconductor Device Comprising a Superlattice Dielectric Interface Layer
Method for Making a Semiconductor Device Including Band-Engineered Superlattice Using Intermediate Annealing
Semiconductor Device Including a Floating Gate Memory Cell with a Superlattice Channel
Semiconductor Device Having a Semiconductor-on-Insulator Configuration and a Superlattice
Semiconductor Device Including a Memory Cell with a Negative Differential Resistance (Ndr) Device
Microelectromechanical Systems (Mems) Device Including a Superlattice
Method for Making a Semiconductor Device Including Shallow Trench Isolation (Sti) Regions with a Superlattice Therebetween
Finfet Including a Superlattice
Method for Making a Semiconductor Device Having a Semiconductor-on-Insulator (Soi) Configuration and Including a Superlattice on a Thin Semiconductor Layer
Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-on Resistance
Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-on Resistance
Method for Making an Electronic Device Including a Poled Superlattice Having a Net Electrical Dipole Moment
Multiple-Wavelength Opto-Electronic Device Including a Superlattice
Method for Making a Multiple-Wavelength Opto-Electronic Device Including a Superlattice
Semiconductor Device Comprising a Lattice Matching Layer
Method for Making a Semiconductor Device Comprising a Lattice Matching Layer
Methods of Making Spintronic Devices with Constrained Spintronic Dopant
Semiconductor Device Including a Metal-to-Semiconductor Superlattice Interface Layer and Related Methods
Semiconductor Device with a Vertical Mosfet Including a Superlattice and Related Methods
Method for Making a Semiconductor Device Including Shallow Trench Isolation (Sti) Regions with Maskless Superlattice Deposition Following Sti Formation and Related Structures
Multiple-Wavelength Opto-Electronic Device Including a Superlattice
Vertical Semiconductor Devices Including Superlattice Punch Through Stop Layer and Related Methods
Semiconductor Devices Including Superlattice Depletion Layer Stack and Related Methods
Semiconductor Devices with Enhanced Deterministic Doping and Related Methods
Application:
62/009,681 →
Semiconductor Device Including a Superlattice and Replacement Metal Gate Structure and Related Methods
Application:
62/083,994 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Mar 17, 2015
From: MEARS TECHNOLOGIES, INC.
To: LIQUID VENTURE PARTNERS, LLC
Reel/Frame 035216/0473 →
Assignment of Assignor's Interest
Jan 27, 2016
From: BTG INTERNATIONAL LIMITED
To: MEARS, ROBERT JOSEPH
Reel/Frame 037597/0168 →
Assignment of Assignor's Interest
Jan 27, 2016
From: MEARS, ROBERT JOSEPH
To: MEARS TECHNOLOGIES, INC.
Reel/Frame 037597/0483 →
Change of Name
Apr 7, 2016
From: BRITISH TECHNOLOGY GROUP LIMITED
To: BTG INTERNATIONAL LIMITED
Reel/Frame 038220/0821 →
Change of Name
Apr 11, 2016
From: MEARS TECHNOLOGIES, INC.
To: ATOMERA INCORPORATED
Reel/Frame 038400/0349 →