IP Library Granted Patent US 6,878,576
Granted Patent B1
US 6,878,576 · App. 10/716,991 · Granted Apr 12, 2005

Method for making semiconductor device including band-engineered superlattice

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Quick Facts
Patent No.
US 6,878,576
App. No.
10/716,991
Granted
Apr 12, 2005
Kind
B1
Abstract

A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

Claims (42)

1. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base germanium monolayers defining a base germanium portion and an energy band-modifying layer thereon;

the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base germanium portions.

2. A method according to claim 1 wherein the superlattice has a common energy band structure therein.

3. A method according to claim 1 wherein the superlattice has a higher charge carrier mobility in at least one direction than would otherwise be present.

4. A method according to claim 3 wherein the higher charge carrier mobility results from a lower conductivity effective mass for the charge carriers in the parallel direction than would otherwise be present.

5. A method according to claim 4 wherein the lower conductivity effective mass is less than two-thirds the conductivity effective mass that would otherwise occur.

6. A method according to claim 3 wherein the charge carriers having the higher mobility comprise at least one of electrons and holes.

7. A method according to claim 1 wherein each energy band-modifying layer comprises oxygen.

8. A method according to claim 1 wherein each energy band-modifying layer is a single monolayer thick.

9. A method according to claim 1 wherein each base germanium portion is less than eight monolayers thick.

10. A method according to claim 1 wherein each base germanium portion is two to six monolayers thick.

11. A method according to claim 1 wherein the superlattice further has a substantially direct energy bandgap.

12. A method according to claim 1 wherein the superlattice further comprises a base germanium cap layer on an uppermost group of layers.

13. A method according to claim 1 wherein all of the base germanium portions are a same number of monolayers thick.

14. A method according to claim 1 wherein at least some of the base germanium portions are a different number of monolayers thick.

15. A method according to claim 1 wherein all of the base germanium portions are a different number of monolayers thick.

16. A method according to claim 1 wherein each non-semiconductor monolayer is thermally stable through deposition of a next layer.

17. A method according to claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

18. A method according to claim 1 further comprising forming the superlattice comprises forming the superlattice on a substrate.

19. A method according to claim 1 further comprising doping the superlattice with at least one type of conductivity dopant therein.

20. A method according to claim 1 wherein the superlattice defines a channel of a transistor.

21. A method for making a semiconductor device comprising:

forming a superlattice comprising a plurality of stacked groups of layers;

each group of layers of the superlattice comprising a plurality of stacked base germanium monolayers being less than eight monolayers to define a base germanium portion, and an energy band-modifying layer thereon;

the energy-band modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base germanium portions.

22. A method according to claim 21 wherein the superlattice has a common energy band structure therein.

23. A method according to claim 21 wherein the superlattice has a higher charge carrier mobility in at least one direction than would otherwise be present.

24. A method according to claim 23 wherein the higher charge carrier mobility results from a lower conductivity effective mass for the charge carriers in the parallel direction than would otherwise be present.

25. A method according to claim 23 wherein the charge carriers having the higher mobility comprise at least one of electrons and holes.

26. A method according to claim 21 wherein each energy band-modifying layer is a single monolayer thick.

27. A method according to claim 21 wherein each base germanium portion is less than eight monolayers thick.

28. A method according to claim 21 wherein each base germanium portion is two to six monolayers thick.

29. A method according to claim 21 wherein the superlattice further has a substantially direct energy bandgap.

30. A method according to claim 21 , wherein the superlattice further comprises a base germanium cap layer on an uppermost group of layers.

31. A method according to claim 21 wherein all of the base germanium portions are a same number of monolayers thick.

32. A method according to claim 21 wherein at least some of the base germanium portions are a different number of monolayers thick.

33. A method according to claim 21 wherein all of the base germanium portions are a different number of monolayers thick.

34. A method according to claim 21 further comprising forming the superlattice comprises forming the superlattice on a substrate.

35. A method according to claim 21 further comprising doping the superlattice with at least one type of conductivity dopant therein.

36. A method according to claim 21 wherein the superlattice defines a channel of a transistor.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Sep 3, 2020
From: CLIFFORD, ROBERT
To: ATOMERA INCORPORATED
Reel/Frame 053681/0942 →
CHANGE OF NAME Recorded Apr 11, 2016
From: MEARS TECHNOLOGIES, INC.
To: ATOMERA INCORPORATED
Reel/Frame 038400/0349 →
SECURITY INTEREST Recorded Mar 17, 2015
From: MEARS TECHNOLOGIES, INC.
To: LIQUID VENTURE PARTNERS, LLC
Reel/Frame 035216/0473 →
CHANGE OF NAME Recorded Aug 21, 2007
From: RJ MEARS, LLC
To: MEARS TECHNOLOGIES, INC.
Reel/Frame 019714/0907 →