Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
View Patent ↗A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
1. A method for making a semiconductor device comprising:
forming an insulating layer on a substrate;
forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate; and
forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer;
the superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions.
2. The method of claim 1 wherein the semiconductor layer and the base semiconductor monolayers each comprises a same semiconductor material.
3. The method of claim 1 wherein the substrate, the semiconductor layer and the base semiconductor monolayers each comprises silicon; and wherein the insulating layer comprises silicon oxide.
4. The method of claim 1 wherein the semiconductor layer has a thickness of less than about 10 nm.
5. The method of claim 1 further comprising:
forming spaced-apart source and drain regions laterally adjacent the superlattice to define a channel therein;
forming a gate dielectric layer overlying the superlattice; and
a gate electrode layer overlying said gate dielectric layer.
6. The method of claim 1 wherein each non-semiconductor layer is a single monolayer thick.
7. The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
8. The method of claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.
9. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
10. The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
11. The method of claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
12. The method of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
13. The method of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
14. The method of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.
15. The method of claim 5 further comprising forming a contact layer on at least one of the source and drain regions.
16. A method for making a semiconductor device comprising:
forming an insulating layer on a substrate;
forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate, the semiconductor layer having a thickness of less than about 10 nm; and
forming a superlattice on the semiconductor layer on a side thereof opposite the insulating layer;
the superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions;
the semiconductor layer and the base semiconductor monolayers each comprising a same semiconductor material.
17. The method of claim 16 wherein the substrate, the semiconductor layer and the base semiconductor monolayers each comprises silicon; and
wherein the insulating layer comprises silicon oxide.
18. The method of claim 16 further comprising:
forming spaced-apart source and drain regions laterally adjacent the superlattice to define a channel therein;
forming a gate dielectric layer overlying the superlattice; and
a gate electrode layer overlying said gate dielectric layer.
19. The method of claim 16 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
20. The method of claim 16 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
21. The method of claim 16 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.