Patent Assignment
Reel/Frame 019817/0236
Change of Name
Recorded: 2007-09-12
Pages: 27
Assignor
RJ MEARS, LLC
Executed: 2007-03-14
Assignee
MEARS TECHNOLOGIES, INC.
1100 WINTER STREET, SUITE 4700, WALTHAM, MASSACHUSETTS, 02451
Covered Properties
(52)
Integrated Circuit Comprising an Active Optical Device Having an Energy Band Engineered Superlattice
Electronic Device Comprising Active Optical Devices with an Energy Band Engineered Superlattice
Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice
Application:
10/936,933 →
Publication:
US 2005/0032247
Integrated Circuit Comprising a Waveguide Having an Energy Band Engineered Superlattice
Method for making electronic device comprising active optical devices with an energy band engineered superlattice
Application:
10/937,072 →
Publication:
US 2005/0029510
Semiconductor Device Comprising a Superlattice Channel Vertically Stepped Above Source and Drain Regions
Method for Making Semiconductor Device Comprising a Superlattice with Upper Portions Extending Above Adjacent Upper Portions of Source and Drain Regions
Semiconductor Device Comprising a Superlattice with Upper Portions Extending Above Adjacent Upper Portions of Source and Drain Regions
Semiconductor Device Including a Mosfet Having a Band-Engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
Method for Making a Semiconductor Device Including a Mosfet Having a Band-Engineered Superlattice with a Semiconductor Cap Layer Providing a Channel
Semiconductor Device Including Mosfet Having Band-Engineered Superlattice
Method for Making a Semiconductor Device Comprising a Superlattice Dielectric Interface Layer
Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
Application:
11/136,748 →
Publication:
US 2005/0282330
Semiconductor device including a superlattice having at least one group of substantially undoped layers
Application:
11/136,757 →
Publication:
US 2005/0279991
Semiconductor device comprising a superlattice dielectric interface layer
Application:
11/136,881 →
Publication:
US 2006/0011905
Semiconductor Device Including a Dopant Blocking Superlattice
Application:
11/380,987 →
Publication:
US 2006/0220118
Method for Making a Semiconductor Device Including a Dopant Blocking Superlattice
Application:
11/380,992 →
Publication:
US 2006/0273299
Semiconductor Device Including a Floating Gate Memory Cell with a Superlattice Channel
Method for Making a Semiconductor Device Including a Floating Gate Memory Cell with a Superlattice Channel
Application:
11/381,794 →
Publication:
US 2006/0263980
Semiconductor Device Having a Semiconductor-on-Insulator Configuration and a Superlattice
Method for Making a Semiconductor Device Having a Semiconductor-on-Insulator Configuration and a Superlattice
Application:
11/381,850 →
Publication:
US 2006/0243964
Semiconductor Device Including a Memory Cell with a Negative Differential Resistance (Ndr) Device
Method for Making a Semiconductor Device Including a Memory Cell with a Negative Differential Resistance (Ndr) Device
Application:
11/420,891 →
Publication:
US 2006/0231857
Microelectromechanical Systems (Mems) Device Including a Superlattice
Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
Application:
11/421,263 →
Publication:
US 2006/0223215
Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
Application:
11/425,201 →
Publication:
US 2006/0267130
Method for Making a Semiconductor Device Including Shallow Trench Isolation (Sti) Regions with a Superlattice Therebetween
Method for Making a FINFET Including a Superlattice
Application:
11/426,976 →
Publication:
US 2006/0292765
Method for Making a Semiconductor Device Having a Semiconductor-on-Insulator (Soi) Configuration and Including a Superlattice on a Thin Semiconductor Layer
Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
Application:
11/428,015 →
Publication:
US 2006/0289049
Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
Application:
11/457,263 →
Publication:
US 2007/0010040
Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
Application:
11/457,276 →
Publication:
US 2007/0015344
Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
Application:
11/457,293 →
Publication:
US 2007/0020860
Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
Application:
11/457,299 →
Publication:
US 2007/0012910
Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
Application:
11/457,315 →
Publication:
US 2007/0020833
Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-on Resistance
Method for Making a Semiconductor Device Including Regions of Band-Engineered Semiconductor Superlattice to Reduce Device-on Resistance
Semiconductor device including a front side strained superlattice layer and a back side stress layer
Application:
11/534,796 →
Publication:
US 2007/0063185
Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
Application:
11/534,819 →
Publication:
US 2007/0063186
Electronic Device Including a Poled Superlattice Having a Net Electrical Dipole Moment
Application:
11/614,477 →
Publication:
US 2007/0158640
Method for Making an Electronic Device Including a Poled Superlattice Having a Net Electrical Dipole Moment
Electronic Device Including a Selectively Polable Superlattice
Application:
11/614,535 →
Publication:
US 2007/0187667
Method for Making an Electronic Device Including a Selectively Polable Superlattice
Application:
11/614,559 →
Publication:
US 2007/0166928
Multiple-Wavelength Opto-Electronic Device Including a Superlattice
Method for Making a Multiple-Wavelength Opto-Electronic Device Including a Superlattice
Semiconductor Device Comprising a Lattice Matching Layer
Method for Making a Semiconductor Device Comprising a Lattice Matching Layer
Spintronic Devices with Constrained Spintronic Dopant
Application:
11/687,422 →
Publication:
US 2008/0012004
Methods of Making Spintronic Devices with Constrained Spintronic Dopant
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 9, 2004
From: MEARS, ROBERT J.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 015784/0090 →
Assignment of Assignor's Interest
Sep 9, 2004
From: MEARS, ROBERT J.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 015785/0225 →
Assignment of Assignor's Interest
Sep 9, 2004
From: MEARS, ROBERT J.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 015785/0189 →
Assignment of Assignor's Interest
Sep 9, 2004
From: MEARS, ROBERT J.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 015783/0871 →
Assignment of Assignor's Interest
Sep 9, 2004
From: MEARS, ROBERT J.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 015783/0429 →
Assignment of Assignor's Interest
Jan 3, 2005
From: KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016117/0806 →
Assignment of Assignor's Interest
Feb 4, 2005
From: KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016239/0096 →
Assignment of Assignor's Interest
Feb 7, 2005
From: KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016291/0509 →
Assignment of Assignor's Interest
Feb 7, 2005
From: KEEPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016242/0387 →
Assignment of Assignor's Interest
Apr 20, 2005
From: MEARS, ROBERT J.; YIPTONG, JEAN AIGUSTIN CHAN FOOK; HYTHA, MAREK; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016477/0963 →
Assignment of Assignor's Interest
Apr 20, 2005
From: MEARS, ROBERT J.; YIPTONG, JEAN AIGUSTIN CHAN SOW FOOK; HYTHA, MAREK; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016478/0469 →
Assignment of Assignor's Interest
Sep 1, 2005
From: MEARS, ROBERT J.; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016989/0718 →
Assignment of Assignor's Interest
Sep 1, 2005
From: MEARS, ROBERT J.; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 016947/0703 →
Assignment of Assignor's Interest
Oct 4, 2005
From: MEARS, ROBERT J.; HYTHA, MAREK; KREPS, SCOTT A.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 017059/0266 →
Assignment of Assignor's Interest
Oct 4, 2005
From: MEARS, ROBERT J.; HYTHA, MAREK; KREPS, SCOTT A.; STEPHENSON, ROBERT JOHN
To: RJ MEARS, LLC
Reel/Frame 017059/0249 →
Re-Record to Correct the Name of the Second Assignor, Previously Recorded on Reel 016477 Frame 0963.
Mar 20, 2006
From: MEARS, ROBERT J.; YIPTONG, JEAN AUGUSTIN CHAN SOW FOOK; HYTHA, MAREK; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 017709/0372 →
Assignment of Assignor's Interest
Jun 26, 2006
From: STEPHENSON, ROBERT JOHN; HYTHA, MAREK
To: RJ MEARS, LLC
Reel/Frame 017844/0284 →
Assignment of Assignor's Interest
Jun 27, 2006
From: KREPS, SCOTT A.; RAO, KALIPATNAM VIVEK
To: RJ MEARS, LLC
Reel/Frame 017850/0761 →
Assignment of Assignor's Interest
Jul 7, 2006
From: KREPS, SCOTT A.; RAO, KALIPATNAM VIVEK
To: RJ MEARS, LLC
Reel/Frame 017891/0529 →
Assignment of Assignor's Interest
Jul 28, 2006
From: KREPS, SCOTT A.; RAO, KALIPATNAM VIVEK
To: RJ MEARS, LLC
Reel/Frame 018017/0991 →
Assignment of Assignor's Interest
Aug 4, 2006
From: STEPHENSON, ROBERT JOHN; HYTHA, MAREK
To: RJ MEARS, LLC
Reel/Frame 018054/0190 →
Security Interest
Mar 17, 2015
From: MEARS TECHNOLOGIES, INC.
To: LIQUID VENTURE PARTNERS, LLC
Reel/Frame 035216/0473 →
Change of Name
Apr 11, 2016
From: MEARS TECHNOLOGIES, INC.
To: ATOMERA INCORPORATED
Reel/Frame 038400/0349 →
Change of Name
Oct 4, 2016
From: MEARS TECHNOLOGIES, INC.
To: ATOMERA INCORPORATED
Reel/Frame 040223/0108 →
Release of Security Interest
Sep 3, 2020
From: CLIFFORD, ROBERT
To: ATOMERA INCORPORATED
Reel/Frame 053681/0942 →