IP Library Patent Application 11426976
Patent Application
App. No. 11/426,976

Method for Making a FINFET Including a Superlattice

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Quick Facts
Patent No.
US None
App. No.
11/426,976
Abstract

A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims (29)

1 . A method for making a semiconductor device comprising:

forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin;

the fin comprising at least one superlattice including a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2 . The method of claim 1 further comprising a substrate supporting the at least one FINFET; and wherein the fin comprises a pair of spaced apart superlattices and a semiconductor layer therebetween with groups of layers of each superlattice being stacked in a lateral direction.

3 . The method of claim 1 further comprising a substrate supporting the at least one FINFET; and wherein the fin comprises a single superlattice with groups of layers stacked in a vertical direction.

4 . The method of claim 1 wherein the substrate comprises an uppermost insulator layer supporting the at least one FINFET.

5 . The method of claim 1 wherein the gate comprises a gate dielectric layer and a gate electrode layer overlying the gate dielectric layer.

6 . The method of claim 1 wherein at least one group of layers of the at least one superlattice is substantially undoped.

7 . The method of claim 1 wherein the base semiconductor comprises silicon.

8 . The method of claim 7 wherein the at least one non-semiconductor monolayer comprises oxygen.

9 . The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.

10 . The method of claim 1 wherein the at least one non-semiconductor monolayer is a single monolayer thick.

11 . The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

12 . The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

13 . The method of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers of the at least one superlattice are chemically bound together.

14 . The method of claim 1 wherein the at least one FINFET comprises a plurality of FINFETs.

15 . The method of claim 1 wherein the plurality of FINFETS have different channel conductivities.

16 . The method of claim 1 wherein forming the at least one FINFET comprises forming a plurality thereof defining an inverter.

17 . A method for making a semiconductor device comprising:

forming at least one fin field-effect transistor (FINFET) adjacent a substrate and comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin;

the fin comprising a pair of spaced apart superlattices and a semiconductor layer therebetween;

each superlattice comprising a plurality of groups of layers stacked in a lateral direction, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

18 . The method of claim 17 wherein the substrate comprises an uppermost insulator layer supporting the at least one FINFET.

19 . The method of claim 17 wherein the at least one FINFET comprises a plurality of FINFETS having different channel conductivities.

20 . A method for making a semiconductor device comprising:

forming at least one fin field-effect transistor (FINFET) adjacent a substrate and comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin;

the fin comprising a superlattice including a plurality of groups of layers stacked in a vertical direction, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

21 . The method of claim 20 wherein the substrate comprises an uppermost dielectric layer supporting the at least one FINFET.

22 . The method of claim 20 wherein the at least one FINFET comprises a plurality of FINFETS having different channel conductivities.

Assignments (2)
CHANGE OF NAME Recorded Sep 12, 2007
From: RJ MEARS, LLC
To: MEARS TECHNOLOGIES, INC.
Reel/Frame 019817/0236 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2006
From: BLANCHARD, RICHARD A.; RAO, KALIPATNAM VIVEK; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 018240/0397 →