Semiconductor device including MOSFET having band-engineered superlattice
View Patent ↗A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.
1. A method for making a semiconductor device comprising:
forming a superlattice comprising a plurality of stacked groups of layers; and
forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers;
each group of layers of the superlattice comprising a plurality of stacked silicon atomic layers defining a silicon portion and an energy band-modifying layer thereon;
the energy-band modifying layer comprising at least one oxygen atomic layer constrained within a crystal lattice of adjacent silicon portions, and at least some silicon atoms from opposing silicon portions being chemically bound together with the chemical bonds traversing the at least one oxygen atomic layer therebetween.
2. A method according to claim 1 wherein the superlattice also has a common energy band structure therein.
3. A method according to claim 1 wherein the superlattice further has a substantially direct energy bandgap.
4. A method according to claim 1 wherein each non-semiconductor monolayer is thermally stable through deposition of a next layer.
5. A method according to claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.
6. A method according to claim 1 wherein all of the base semiconductor portions are a same number of atomic layers thick.
7. A method according to claim 1 wherein at least some of the base semiconductor portions are a different number of atomic layers thick.
8. A method according to claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
9. A method according to claim 1 wherein forming the superlattice comprises forming the superlattice on a substrate.
10. A method according to claim 1 further comprising doping the superlattice with at least one type of conductivity dopant therein.
11. A method according to claim 1 wherein the superlattice defines a channel for the semiconductor device and wherein forming the regions comprises:
forming source and drain regions laterally adjacent the superlattice channel; and
forming a gate overlying the superlattice channel.