METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL
A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one non-volatile memory cell. Spaced apart source and drain regions may be formed, and a superlattice channel may be formed between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers on the substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be formed adjacent the superlattice channel, and a control gate may be formed adjacent the floating gate.
1 . A method for making a semiconductor device comprising:
providing a semiconductor substrate; and
forming at least one non-volatile memory cell by
forming spaced apart source and drain regions,
forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions,
each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,
the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming a floating gate adjacent the superlattice channel, and
forming a control gate adjacent the floating gate.
2 . The method of claim 1 wherein forming the at least one non-volatile memory cell further comprises forming a first insulating layer between the floating gate and the control gate.
3 . The method of claim 2 wherein forming the at least one non-volatile memory cell further comprises forming a second insulating layer between the superlattice channel and the floating gate.
4 . The method of claim 1 wherein forming the at least one non-volatile memory cell further comprises forming a superlattice insulating layer between the floating gate and the control gate.
5 . The method of claim 1 further comprising forming a contact layer on at least one of the source and drain regions.
6 . The method of claim 1 wherein the superlattice channel has a common energy band structure therein.
7 . The method of claim 1 wherein the superlattice channel has a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer.
8 . The method of claim 1 wherein each base semiconductor portion comprises silicon.
9 . The method of claim 1 wherein each base semiconductor portion comprises germanium.
10 . The method of claim 1 wherein each energy band-modifying layer comprises oxygen.
11 . The method of claim 1 wherein each energy band-modifying layer is a single monolayer thick.
12 . The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
13 . The method of claim 1 wherein the superlattice channel further has a substantially direct energy bandgap.
14 . The method of claim 1 wherein forming the superlattice channel further comprises forming a base semiconductor cap layer on an uppermost group of layers.
15 . The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
16 . The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
17 . The method of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
18 . A method for making a semiconductor device comprising:
providing a semiconductor substrate; and
forming at least one non-volatile memory cell by
forming spaced apart source and drain regions,
forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions,
each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,
the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, the superlattice channel having a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer,
forming a floating gate adjacent the first insulating layer,
forming an insulating layer adjacent superlattice channel, and
forming a control gate adjacent the insulating layer.
19 . The method of claim 13 wherein forming the at least one non-volatile memory cell further comprises forming a second insulating layer between the superlattice channel and the floating gate.
20 . The method of claim 18 wherein the superlattice channel has a common energy band structure therein.
21 . The method of claim 18 wherein each base semiconductor portion comprises silicon.
22 . The method of claim 18 wherein each energy band-modifying layer comprises oxygen.
23 . A method for making a semiconductor device comprising:
providing a semiconductor substrate; and
forming at least one non-volatile memory cell by
forming spaced apart source and drain regions,
forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions,
each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,
the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and the superlattice channel having a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer,
forming a floating gate adjacent the superlattice channel,
forming a superlattice insulating layer adjacent the floating gate, and
forming a control gate adjacent the superlattice insulating layer.
24 . The method of claim 32 wherein the superlattice channel has a common energy band structure therein.
25 . The method of claim 32 wherein each base semiconductor portion comprises silicon.
26 . The method of claim 32 wherein each energy band-modifying layer comprises oxygen.
27 . A method for making a semiconductor device comprising:
providing a semiconductor substrate; and
forming at least one non-volatile memory cell by
forming spaced apart source and drain regions,
forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions,
each group of layers of the superlattice channel comprising a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon,
the energy band-modifying layer comprising at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming a floating gate adjacent the superlattice channel, and
forming a control gate adjacent the floating gate.
28 . The method of claim 27 wherein forming the at least one non-volatile memory cell further comprises forming a first insulating layer between the floating gate and the control gate.
29 . The method of claim 28 wherein forming the at least one non-volatile memory cell further comprises forming a second insulating layer between the superlattice channel and the floating gate.
30 . The method of claim 27 wherein forming the at least one non-volatile memory cell further comprises forming a superlattice insulating layer between the floating gate and the control gate.
31 . The method of claim 27 wherein the superlattice channel has a common energy band structure therein.
32 . The method of claim 27 wherein the superlattice channel has a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer.