IP Library Patent Application 11457299
Patent Application
App. No. 11/457,299

Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer

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Quick Facts
Patent No.
US None
App. No.
11/457,299
Abstract

A semiconductor device may include a semiconductor substrate, and at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon. The MOSFET may include spaced-apart source and drain regions, a channel between the source and drain regions, and a gate overlying the channel defining an interface therewith. The gate may include a gate dielectric overlying the channel and a gate electrode overlying the gate dielectric. The channel may include a plurality of stacked base semiconductor monolayers, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers. The at least one non-semiconductor monolayer may be positioned at depth of about 4-100 monolayers relative to the interface between the channel and the gate dielectric.

Claims (24)

1 . A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon comprising

spaced-apart source and drain regions,

a channel between the source and drain regions, said channel comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor monolayers, and

a gate overlying said channel and defining an interface therewith, said gate comprising a gate dielectric overlying said channel and a gate electrode overlying said gate dielectric;

said at least one non-semiconductor monolayer being positioned at depth of about 4-100 monolayers relative to the interface between said channel and said gate dielectric.

2 . The semiconductor device of Claim 1 wherein said at least one non-semiconductor monolayer is positioned at a depth of about 4 to 30 monolayers relative to the interface between said channel and said gate dielectric.

3 . The semiconductor device of claim 1 wherein each base semiconductor monolayer comprises silicon.

4 . The semiconductor device of claim 1 wherein each base semiconductor monolayer comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

5 . The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises oxygen.

6 . The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

7 . The semiconductor device of claim 1 wherein adjacent base semiconductor monolayers on opposing sides of said at least one non-semiconductor layer are chemically bound together.

8 . The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a single non-semiconductor monolayer.

9 . A semiconductor device comprising:

a semiconductor substrate; and

at least one metal oxide semiconductor field-effect transistor (MOSFET) thereon comprising

spaced-apart source and drain regions,

a channel between the source and drain regions, said channel comprising a plurality of stacked base silicon monolayers and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon monolayers, and

a gate overlying said channel and defining an interface therewith, said gate comprising a gate dielectric overlying said channel and a gate electrode overlying said gate dielectric;

said at least one oxygen monolayer being positioned at depth of about 4-100 monolayers relative to the interface between said channel and said gate dielectric.

10 . The semiconductor device of claim 9 wherein said at least one oxygen monolayer is positioned at a depth of about 4 to 30 monolayers relative to the interface between said channel and said gate dielectric.

11 . The semiconductor device of claim 9 wherein adjacent base silicon monolayers on opposing sides of said at least one non-semiconductor layer are chemically bound together.

12 . The semiconductor device of claim 9 wherein said at least one oxygen monolayer comprises a single oxygen monolayer.

Assignments (2)
CHANGE OF NAME Recorded Sep 12, 2007
From: RJ MEARS, LLC
To: MEARS TECHNOLOGIES, INC.
Reel/Frame 019817/0236 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2006
From: MEARS, ROBERT J.; HYTHA, MAREK; KREPS, SCOTT A.
To: RJ MEARS, LLC
Reel/Frame 018340/0941 →