METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
A method for making a semiconductor device may include forming at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1 . A method for making a semiconductor device comprising:
forming at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto;
the NDR device comprising a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
2 . The method of claim 1 wherein the NDR device comprises a thyristor.
3 . The method of claim 2 wherein the thyristor comprises a plurality of stacked semiconductor layers having alternating first and second conductivity types; and wherein an uppermost layer of the stack of semiconductor layers comprises the superlattice.
4 . The method of claim 3 wherein at least one other layer of the plurality of stacked semiconductor layers beneath the uppermost layer also comprises the superlattice.
5 . The method of claim 3 wherein the thyristor further comprises a voltage reference contact on the uppermost layer of the plurality of stacked semiconductor layers.
6 . The method of claim 1 wherein forming the at least one memory cell further comprises coupling at least one access transistor to the NDR device.
7 . The method of claim 1 wherein forming the at least one memory cell comprises forming a plurality thereof.
8 . The method of claim 1 wherein the base semiconductor comprises silicon.
9 . The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
10 . The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.
11 . The method of claim 1 wherein the at least one non-semiconductor monolayer is a single monolayer thick.
12 . The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
13 . The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
14 . The method of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers of the at least one superlattice are chemically bound together.
15 . A method for making a semiconductor device comprising:
forming at least one memory cell comprising a thyristor, a control gate coupled to the thyristor, and an access transistor coupled to the thyristor;
the thyristor comprising a plurality of stacked semiconductor layers having alternating first and second conductivity types, and at least one layer of the stack of semiconductor layers comprising a superlattice;
the superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
16 . The method of claim 15 wherein the at least one layer of the stack of semiconductor layers comprises an uppermost layer of the plurality of stacked semiconductor layers.
17 . The method of claim 16 wherein the thyristor further comprises a voltage reference contact on the uppermost layer of the plurality of stacked semiconductor layers.
18 . The method of claim 15 wherein the base semiconductor comprises silicon; and wherein the at least one non-semiconductor monolayer comprises oxygen.
19 . The method of claim 15 wherein opposing base semiconductor portions in adjacent groups of layers of the at least one superlattice are chemically bound together.
20 . A method for making a semiconductor device comprising:
forming a thyristor comprising plurality of stacked semiconductor layers having alternating first and second conductivity types; and
coupling a control gate to the thyristor;
at least one of the layers of the stack of semiconductor layers comprising a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
21 . The method of claim 20 wherein the at least one layer of the stack of semiconductor layers comprises an uppermost layer of the plurality of stacked semiconductor layers.
22 . The method of claim 21 wherein the thyristor further comprises a voltage reference contact on the uppermost layer of the plurality of stacked semiconductor layers.
23 . The method of claim 20 wherein the base semiconductor comprises silicon; and wherein the at least one non-semiconductor monolayer comprises oxygen.
24 . The method of claim 20 wherein opposing base semiconductor portions in adjacent groups of layers of the superlattice are chemically bound together.