Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
View Patent ↗A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions. The method may further include selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.
1. A method for making a semiconductor device comprising:
forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate;
depositing a plurality of layers over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions, each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions; and
selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.
2. The method according to claim 1 wherein the at least one AA mask comprises a single baseline AA mask.
3. The method according to claim 1 wherein selectively removing comprises:
patterning a photoresist layer with the at least one AA mask to expose the non-monocrystalline regions; and
performing at least one plasma etching of the exposed non-monocrystalline regions.
4. The method according to claim 1 wherein each non-semiconductor layer is a single monolayer thick.
5. The method according to claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
6. The method according to claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.
7. The method according to claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.
8. The method according to claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
9. The method according to claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
10. The method according to claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
11. The method according to claim 1 wherein each non-semiconductor layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
12. The method according to claim 1 wherein opposing base semiconductor portions in adjacent groups of layers are chemically bound together.
13. method for making a semiconductor CMOS device comprising:
forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate;
depositing a plurality of layers over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions, each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions;
selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask; and
forming a plurality of NMOS and PMOS transistor channels associated with the superlattices and defining a CMOS device.
14. The method according to claim 13 wherein the at least one AA mask comprises a single baseline AA.
15. The method according to claim 13 wherein the at least one AA mask comprises a first oversized channel-stop AA mask for NMOS transistors and a second oversized channel-stop AA mask for PMOS transistors.
16. The method according to claim 15 further comprising performing a first channel-stop implant using the first oversized channel-stop AA mask, and performing a second channel-stop implant using the second oversized channel-stop AA mask.
17. The method according to claim 16 further comprising performing a first etch prior to the first channel-stop implant and performing a second etch prior to the second channel-stop implant.
18. The method according to claim 15 wherein non-monocrystalline stringers are formed in divots in the STI regions; and further comprising performing at least a partial etch of the non-monocrystalline stringers.
19. The method according to claim 13 wherein selectively removing comprises:
patterning a photoresist layer with the at least one AA mask to expose the non-monocrystalline regions; and
performing at least one plasma etching of the exposed non-monocrystalline regions.
20. The method according to claim 13 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors; and wherein each non-semiconductor layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.