Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
View Patent ↗A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
1. A semiconductor device comprising:
a substrate;
spaced apart source and drain regions defining a channel region therebetween in said substrate;
said substrate having a plurality of spaced apart superlattices in the drain region;
each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions;
wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween.
2. The semiconductor device of claim 1 wherein said plurality of spaced apart superlattices also extend into the channel region.
3. The semiconductor device of claim 1 wherein said source and drain regions are laterally spaced apart.
4. The semiconductor device of claim 1 wherein said source and drain regions are vertically spaced apart.
5. The semiconductor device of claim 1 wherein said spaced apart superlattices extend laterally between said source and drain regions.
6. The semiconductor device of claim 1 wherein said spaced apart superlattices extend vertically between said source and drain regions.
7. The semiconductor device of claim 1 wherein said spaced apart superlattices are substantially parallel to one another.
8. The semiconductor device of claim 1 further comprising a gate dielectric layer adjacent the channel region, and a gate electrode layer adjacent said gate dielectric layer.
9. The semiconductor device of claim 1 wherein said base semiconductor portions comprise silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.
10. The semiconductor device of claim 1 wherein each non-semiconductor layer is a single monolayer thick.
11. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
12. The semiconductor device of claim 1 wherein each superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.
13. The semiconductor device of claim 1 wherein all of the base semiconductor portions are the same number of monolayers thick.
14. The semiconductor device of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.
15. The semiconductor device of claim 1 wherein all of the base semiconductor portions are a different number of monolayers thick.
16. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
17. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
18. A semiconductor device comprising:
a substrate;
spaced apart source and drain regions defining a channel region therebetween in said substrate;
said substrate having a plurality of spaced apart superlattices in the channel region; and
each superlattice comprising a plurality of stacked groups of layers with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon, and with the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions;
wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween.
19. The semiconductor device of claim 18 wherein said source and drain regions are laterally spaced apart.
20. The semiconductor device of claim 18 wherein said source and drain regions are vertically spaced apart.
21. The semiconductor device of claim 18 wherein said spaced apart superlattices extend laterally between said source and drain regions.
22. The semiconductor device of claim 18 wherein said spaced apart superlattices extend vertically between said source and drain regions.
23. The semiconductor device of claim 18 wherein said spaced apart superlattices are substantially parallel to one another.
24. The semiconductor device of claim 18 further comprising a gate dielectric layer adjacent the channel region, and a gate electrode layer adjacent said gate dielectric layer.
25. The semiconductor device of claim 18 wherein said base semiconductor portions comprise silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.