Semiconductor device including a strained superlattice and overlying stress layer and related methods
View Patent ↗A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1. A semiconductor device comprising:
a strained superlattice layer comprising a plurality of stacked groups of layers;
non-superlattice regions for causing transport of charge carriers through said strained superlattice layer in a parallel direction relative to the stacked groups of layers; and
a stress layer above said strained superlattice layer;
each group of layers of said strained superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and a single non-semiconductor monolayer constrained inside a crystal lattice of adjacent base semiconductor portions in the stacked base semiconductor monolayers, at least some semiconductor atoms from opposing base semiconductor portions in the stacked base semiconductor monolayers being directly chemically bound together, and the chemical bonds traversing the single non-semiconductor monolayer therebetween,
wherein the non-superlattice regions form source and drain regions with the strained superlattice layer therebetween.
2. The semiconductor device of claim 1 wherein said stress layer comprises silicon and nitrogen.
3. The semiconductor device of claim 1 further comprising a semiconductor substrate adjacent said strained superlattice layer on a side thereof opposite said stress layer.
4. The semiconductor device of claim 1 wherein said strained superlattice layer has a compressive strain.
5. The semiconductor device of claim 1 wherein said strained superlattice layer has a tensile strain.
6. The semiconductor device of claim 1 wherein said strained superlattice layer has a common energy band structure therein.
7. The semiconductor device of claim 1 wherein each of the base semiconductor portions comprises silicon.
8. The semiconductor device of claim 1 wherein each of the base semiconductor portions comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.
9. The semiconductor device of claim 1 wherein each of the non-semiconductor monolayers comprises oxygen.
10. The semiconductor device of claim 1 wherein each of the non-semiconductor monolayers comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
11. The semiconductor device of claim 1 wherein each of the base semiconductor portions is less than eight monolayers thick.
12. The semiconductor device of claim 1 wherein said strained superlattice layer further has a substantially direct energy bandgap.
13. The semiconductor device of claim 1 wherein said strained superlattice layer further comprises a base semiconductor cap layer on an uppermost group of layers.
14. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.
15. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.