Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
View Patent ↗A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1. A semiconductor device comprising:
a substrate;
an insulating layer adjacent said substrate;
a semiconductor layer adjacent a face of said insulating layer opposite said substrate;
a superlattice adjacent said semiconductor layer and extending between said source and drain regions to define a channel, said superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon;
spaced apart source and drain regions on said semiconductor layer for causing transport of charge carriers through said superlattice in a parallel direction relative to the stacked groups of layers; and
a gate overlying said superlattice;
said energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween.
2. The semiconductor device of claim 1 further comprising a contact layer on at least one of said source and drain regions.
3. The semiconductor device of claim 1 wherein said substrate comprises silicon, and wherein said insulating layer comprises silicon oxide.
4. The semiconductor device of claim 1 wherein said superlattice has a common energy band structure therein.
5. The semiconductor device of claim 1 wherein said superlattice has a higher charge carrier mobility than would otherwise be present without said energy band-modifying layer.
6. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.
7. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.
8. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises oxygen.
9. The semiconductor device of claim 1 wherein each energy band-modifying layer is a single monolayer thick.
10. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.
11. The semiconductor device of claim 1 wherein said superlattice further has a substantially direct energy bandgap.
12. The semiconductor device of claim 1 wherein said superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.
13. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.
14. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.
15. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
16. A method for making a semiconductor device comprising:
forming an insulating layer adjacent a substrate;
forming a semiconductor layer adjacent a face of the insulating layer opposite the substrate
forming a superlattice adjacent the semiconductor layer, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon;
forming source and drain regions on the semiconductor layer so that the superlattice extends therebetween to define a channel, the source and drain regions for causing transport of charge carriers through said superlattice in a parallel direction relative to the stacked groups of layers; and
forming a gate overlying the superlattice;
the energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween.
17. The method of claim 16 further comprising forming a contact layer on at least one of the source and drain regions.
18. The method of claim 16 wherein the substrate comprises silicon, and wherein the insulating layer comprises silicon oxide.
19. The method of claim 16 wherein the superlattice has a common energy band structure therein.
20. The method of claim 1 wherein the superlattice has a higher charge carrier mobility than would otherwise be present without the energy band-modifying layer.
21. The method of claim 1 wherein each base semiconductor portion comprises silicon.
22. The method of claim 1 wherein each base semiconductor portion comprises germanium.
23. The method of claim 1 wherein each energy band-modifying layer comprises oxygen.