Vertical semiconductor devices including superlattice punch through stop layer and related methods
View Patent ↗A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
1. A method for making a semiconductor device comprising:
forming a plurality of fins on a substrate by
forming a superlattice layer on the substrate,
epitaxially growing a bulk semiconductor layer on the superlattice layer, and
etching a plurality of spaced apart trenches extending through the bulk semiconductor layer, the superlattice layer, and into the substrate to simultaneously define respective lower semiconductor fin portions, superlattice punch-through stop layers, and upper semiconductor fin portions in each fin,
each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming source and drain regions at opposing ends of the fins; and
forming a gate overlying the fins.
2. The method of claim 1 wherein forming the at least one respective superlattice punch-through stop layer comprises forming a respective plurality of vertically stacked superlattice punch-through stop layers on each of the lower fin portions with a respective semiconductor layer between each of the superlattice punch-through stop layers.
3. The method of claim 1 further comprising forming an insulating layer on the substrate surrounding the lower semiconductor fin portions.
4. The method of claim 1 further comprising performing a thermal anneal after forming the plurality of fins.
5. The method of claim 1 wherein each base semiconductor portion comprises silicon.
6. The method of claim 1 wherein each base semiconductor portion comprises germanium.
7. The method of claim 1 wherein the at least one non-semiconductor, layer comprises oxygen.
8. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
9. The method of claim 1 wherein the gate comprises an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.
10. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.