Semiconductor integrated circuit device having memory macros and logic cores on board
View Patent ↗A semiconductor integrated circuit device has memory macros and logic cores. The memory macro is composed of a dynamic memory including an access port and a refresh port. The semiconductor integrated circuit device also has a refresh control circuit common for a plurality of the memory macros. The refresh control circuit has a refresh address generation circuit which generates a refresh address for a memory macro having the largest capacity, supplies the refresh address to the memory macro, and supplies given top bits of the refresh address as a refresh address to another memory macro having a smaller capacity.
1. A semiconductor integrated circuit device, comprising:
at least two memory macros having different memory capacities and each comprising a dynamic memory including at least an access port and a refresh port; and
logic cores.
2. The semiconductor integrated circuit device of claim 1 , wherein:
the at least two memory macros and the logic cores constitute a plurality of pairs, and
the semiconductor integrated circuit further comprises a refresh control circuit common for the plurality of pairs.
3. The semiconductor integrated circuit device of claim 2 , wherein:
the at least two memory macros comprise a first memory macro and a second memory macro, the second memory macro having a smaller memory capacity than the first memory macro, and
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for the first memory macro, supplying the refresh address to the first memory macro, and supplying a portion only of bits included in the refresh address as a refresh address to the second memory macro having the smaller capacity.
4. The semiconductor integrated circuit device of claim 2 , wherein
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for a first memory macro of said at least two memory macros, supplying the refresh address to the first memory macro, and supplying only given top bits of the refresh address as a refresh address to a second memory macro of said at least two memory macros having a smaller capacity than the first memory macro.
5. The semiconductor integrated circuit device of claim 2 , wherein:
a second memo macro of said at least two memory macros having a smaller capacity than a first memory macro of said at least two memory macros comprises a frequency divider circuit,
the refresh control circuit comprises a timer circuit generating a refresh start trigger signal that triggers a start of a refresh operation for the first memory macro and supplying the refresh start trigger signal to the first memory macro and the frequency divider circuit of the second memory macro, and
the frequency divider circuit generates a refresh start trigger signal for the second memory macro by dividing a frequency of the refresh start trigger signal supplied from the timer circuit and supplies the generated refresh start trigger signal to the second memory macro.
6. A semiconductor integrated circuit device of claim 2 , wherein:
a second memory macro of said at least two memory macros having a smaller capacity than a first memory macro of said at least two memory macros comprises a frequency divider circuit,
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for the first memory macro, supplying the refresh address to the first memory macro, and supplying part of bits included in the refresh address as a refresh address to the second memory macro having the smaller capacity than the first memory macro and a timer circuit generating a refresh start trigger signal that triggers a start of a refresh operation for the first memory macro and supplying the refresh start trigger signal to the first memory macro and the frequency divider circuit of the second memory macro, and
the frequency divider circuit generates a refresh start trigger signal for the second memory macro by dividing a frequency of the refresh start trigger signal supplied from the timer circuit and supplies the generated refresh start trigger signal to the second memory macro.
7. A semiconductor integrated circuit device of claim 2 , wherein:
a second memory macro of said at least two memory macros having a smaller capacity than a first memory macro of said at least two memory macros comprises a frequency divider circuit, the refresh control circuit comprising:
a refresh address generation circuit generating a refresh address for the first memory macro, supplying the refresh address to the first memory macro, and supplying given top bits of the refresh address as a refresh address to the second memory macro having the smaller capacity than the first memory macro; and
a timer circuit generating a refresh start trigger signal that triggers a start of a refresh operation for the first memory macro and supplying the refresh start triggers concurrently to the first memory macro and the frequency divider circuit of the second memory macro; and
the frequency divider circuit generates a refresh start trigger signal for the second memory macro by dividing a frequency of the refresh start trigger signal supplied from the timer circuit and supplies the generated refresh start trigger signal to the second memory macro.
8. A semiconductor integrated circuit device of claim 2 , wherein:
the at least two memory macros comprise at least a first memory macro and a second memory macro, said second memory macro having a smaller capacity than a capacity of the first memory macro,
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for the second memory macro and supplying the refresh address to the first memory macro and the second memory macro, and
the first memory macro comprises a refresh decoder generating a refresh address selecting a plurality of word lines according to the refresh address supplied from the refresh address generation circuit.
9. A semiconductor integrated circuit device of claim 2 , wherein:
the at least two memory macros comprise at least a first memory macro, a second memory macro having a smaller capacity than a capacity of the first memory macro, and a third memory macro having a smaller capacity than the capacity of the second memory macro,
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for the second memory macro, supplying the refresh address to the first memory macro and the second memory macro, and supplying part of bits of the refresh address to the third memory macro, and
the first memory macro comprises a refresh decoder generating a refresh address selecting a plurality of word lines according to the refresh address supplied from the refresh address generation circuit.
10. A semiconductor integrated circuit device of claim 2 , wherein:
the at least two memory macros comprise at least a first memory macro, a second memory macro having a smaller capacity than a capacity of the first memory macro, and a third memory macro having a smaller capacity than the capacity of the second memory macro,
the refresh control circuit comprises a refresh address generation circuit generating a refresh address for the second memory macro, supplying the refresh address to the first memory macro and the second memory macro, and supplying given top bits of the refresh address to the third memory macro, and
the first memory macro comprises a refresh decoder generating a refresh address selecting a plurality of word lines according to the refresh address supplied from the refresh address generation circuit.
11. A semiconductor integrated circuit device, comprising:
a plurality of memory arrays comprising:
a plurality of memory macros, at least two memory macros having different capacities and each including an access port and a refresh port; and
logic cores, each logic core being paired with a single memory macro; and
a refresh control circuit common for each memory array.
12. A semiconductor integrated circuit device of claim 11 , wherein
the memory macros and the logic cores constitute a plurality of pairs; and
the semiconductor integrated circuit further comprises a power supply circuit common for the plurality of pairs of memory macros and logic cores.
13. A semiconductor integrated circuit device of claim 11 , wherein
all memory macros included in the semiconductor integrated circuit device are comprised of a dynamic memory.
14. A semiconductor integrated circuit device of claim 13 , wherein:
the memory macros and the logic cores constitute a plurality of pairs, and
the semiconductor integrated circuit further comprises a power supply circuit common for the plurality of pairs of memory macros and logic cores.
15. A semiconductor integrated circuit device of claim 13 , wherein
all memory macros included in the semiconductor integrated circuit device are comprised of a dynamic memory at least including an access port and a refresh port.
16. A semiconductor integrated circuit device of claim 11 , wherein the refresh control circuit comprises a refresh address generation circuit generating a refresh address for a first memory macro of each memory array, supplying the refresh address to the first memory macro, and supplying part of bits included in the refresh address as a refresh address to a second memory macro of said each memory array having a smaller capacity than the first memory macro.
17. A semiconductor integrated circuit device, comprising:
a plurality of memory arrays, each memory array comprising:
a plurality of memory macros having different capacities and at least including a memory cell array, a read/write decoder, and a refresh decoder; and
a plurality of logic cores, each logic core being paired with a single memory macro.
18. A semiconductor integrated circuit device of claim 17 , further comprising:
a refresh control circuit common for each memory array, each refresh control circuit providing refresh addresses and refresh trigger signals to the refresh decoders.
19. A semiconductor integrated circuit device of claim 17 , wherein the memory cell array comprises dynamic memory.
20. A semiconductor integrated circuit device, comprising:
a first memory macro and a second memory macro, each of said first and second memory macros including a plurality of dynamic memory cells and logic core, said first memory macro having a memory capacity larger than a memory capacity of said second memory macro; and
a refresh control circuit coupled in common to said first and second memory macros for performing a refresh operation to said first and second memory macros,
wherein said refresh control circuit contains a refresh address generator generating a refresh address to apply said refresh address to said first and second memory macros, and
wherein said first memory macro operates said refresh operation based on said refresh address and said second memory macro operates said refresh operation based on a portion of said refresh address.
21. The device as claimed in claim 20 , wherein an entirety of said refresh address is supplied to said first memory macro and only a portion of said refresh address is supplied to said second memory macro.
22. The device as claimed in claim 20 , wherein said logic core of said first memory core includes a first refresh decoder receiving a refresh address signal and a refresh start trigger signal, said logic core of said second memory core includes a second refresh decoder receiving said refresh address signal and a frequency-divided version of said refresh start trigger signal.
23. The device as claimed in claim 20 , wherein said first and second memory macros include an access port and a refresh port.