Spread spectrum type clock generation circuit for improving frequency modulation efficiency
The present invention provides a spread spectrum type clock generation circuit whose EMI for peripheral equipment is reduced. The clock generation circuit comprises a phase-locked loop circuit and a clock modulation circuit. The clock modulation circuit comprises a ΔΣ modulator, to frequency-modulate an output clock by modulating the frequency division number of a frequency divider in the phase-locked loop circuit by a digital circuit, and further comprises a modulation pattern controller for distributing the peak of a triangular waveform which is a modulation waveform generated by a modulation pattern generator to change the amplitude and the period thereof, thereby making it possible to eliminate dullness and distortion of a modulation waveform in a modulating method using a conventional analog circuit and to obtain an output clock having higher modulation efficiency than that in a case where a normal triangular waveform is employed in a conventional modulating method using a digital circuit.
1. A spread spectrum type clock generation circuit, comprising:
a phase-locked loop circuit including:
a voltage controlled oscillator for generating a clock signal;
a frequency divider for dividing a frequency of the clock signal; and
a phase frequency comparator for comparing an output signal of the frequency divider with a comparison frequency signal obtained by converting an external reference signal; and
a clock modulation circuit being operated based on the clock signal with an intermediate divided number of frequencies from the frequency divider, the clock modulation circuit controlling a frequency division number of the frequency divider by using a given modulation pattern, the clock modulation circuit including a modulation pattern controller for controlling the modulation pattern so as to distribute a peak portion of the modulation pattern.
2. The spread spectrum type clock generation circuit according to claim 1 , wherein the clock modulation circuit comprises:
a modulation pattern generator for generating a digital signal with the modulation pattern;
a gain offset controller for adding a predetermined gain and offset to the digital signal; and
a ΔΣ modulator for generating the digital signal with few bits by adding a quantization noise to the digital signal output from the gain offset controller.
3. The spread spectrum type clock generation circuit according to claim 1 , wherein the phase-locked loop circuit comprises:
a reference frequency divider for converting the external reference signal into the comparison frequency signal having a predetermined frequency;
a charge pump for generating a charge amount corresponding to a phase error signal generated by comparing respective phases of the output signal of the frequency divider and the comparison frequency signal in the phase frequency comparator; and
a loop filter inserted between an output terminal of the charge pump and a particular potential.
4. The spread spectrum type clock generation circuit according to claim 3 , wherein the loop filter comprises:
a first capacitance and a resistance which are connected in series with a power supply voltage or ground; and
a second capacitance connected in parallel with the first capacitance and the resistance.
5. The spread spectrum type clock generation circuit according to claim 4 , wherein the second capacitance has a capacitance value which is not less than one-tenth of another capacitance value of the first capacitance.
6. A spread spectrum type clock generation circuit, comprising:
a phase-locked loop circuit including:
a voltage controlled oscillator for generating a clock signal;
a frequency divider for dividing a frequency of the clock signal; and
a phase frequency comparator for comparing an output signal of the frequency divider with a comparison frequency signal obtained by converting an external reference signal; and
a clock modulation circuit being operated based on the clock signal with an intermediate divided number of frequencies from the frequency divider, the clock modulation circuit controlling a frequency division number of the frequency divider by using a given modulated triangular waveform, the clock modulation circuit including a modulation pattern controller for controlling a number of steps in the triangular waveform, a step width and an offset of the triangular waveform, so as to distribute a peak portion of the modulation pattern.