Floating body-type DRAM cell with increased capacitance
A semiconductor memory device includes transistors, each including a first-conductivity-type semiconductor layer formed on a semiconductor substrate via a first insulating film, a second-conductivity-type source/drain regions formed in the semiconductor layer, a first-conductivity-type body region formed between the source region and the drain region in the semiconductor layer, the body region being electrically floating, and a gate electrode formed on a surface of a central portion of the body region via a second insulating film. In a section along a word line, which connects the gate electrodes together, a length of a boundary between the central portion of the body region and the second insulating film is smaller than a length of a boundary between the body region and the first insulating film. A second-conductivity-type counter impurity is doped in a surface portion of the central portion of the body region on which the second insulating film is formed.
1. A semiconductor memory device with floating body cells comprising:
a plurality of transistors to constitute said floating body cells each having
a semiconductor substrate,
a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystalline structure,
a second-conductivity-type source region and a second-conductivity-type drain region formed in said semiconductor layer,
a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and said body region being electrically floating, and
a gate electrode formed on a surface of a central portion of said body region via a second insulating film;
an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors;
a word line which connects said gate electrodes of said plurality of transistors together;
a bit line electrically connected to said drain region; and
a source line electrically connected to said source region,
wherein in a section along said word line, a length of a boundary between the central portion of said body region and said second insulating film is smaller than a length of a boundary between said body region and said first insulating film;
wherein a second-conductivity-type counter impurity is doped in a surface portion of the central portion of the body region on which said second insulating film is formed.
2. A device according to claim 1 , wherein in the central portion of said body region, boron is doped as the first-conductivity-type impurity, and arsenic is doped as the counter impurity.
3. A device according to claim 1 , wherein said floating body cell has a first data state in which majority carriers are accumulated in said body region, and a second data state in which the majority carriers accumulated in said body region are emitted.
4. A device according to claim 1 , wherein said body region consists of a central portion and a pair of end portions, a top surface of the central portion being covered with a second insulating film on which a gate electrode is formed, said central portion and said pair of end portions being formed along said word line direction.
5. A device according to claim 1 , wherein a bottom surface of said element isolation insulating film is in contact with said first insulating film.
6. A semiconductor memory device with floating body cells comprising:
a plurality of transistors to constitute said floating body cells each having
a semiconductor substrate,
a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystalline structure,
a second-conductivity-type source region and a second-conductivity-type drain region formed in said semiconductor layer,
a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and said body region being electrically floating, and
a gate electrode formed on a surface of a central portion of said body region via a second insulating film;
an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors;
a word line which connects said gate electrodes of said plurality of transistors together;
a bit line electrically connected to said drain region; and
a source line electrically connected to said source region,
wherein in a section along said word line, a length of a boundary between the central portion of said body region said second insulating film is smaller than a length of a boundary between said body region and said first insulating film;
wherein a net impurity concentration in a surface portion of the central portion of the body region on which said second insulating film is formed is lower than a net impurity concentration in a region except for the surface portion.
7. A device according to claim 6 , wherein said floating body cell has a first data state in which majority carriers are accumulated in said body region, and a second data state in which the majority carriers accumulated in said body region are emitted.
8. A device according to claim 6 , wherein said body region consists of a central portion and a pair of end portions, a top surface of the central portion being covered with a second insulating film on which a gate electrode is formed, said central portion and said pair of end portions being formed along said word line direction.
9. A device according to claim 6 , wherein a bottom surface of said element isolation insulating film is in contact with said first insulating film.
10. A semiconductor memory device with floating body cells comprising:
a plurality of transistors to constitute said floating body cells each having
a semiconductor substrate,
a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystalline structure,
a second-conductivity-type source region and a second-conductivity-type drain region formed in said semiconductor layer,
a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and said body region being electrically floating, and
a gate electrode formed on a surface of a central portion of said body region via a second insulating film;
an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors;
a word line which connects said gate electrodes of said plurality of transistors together;
a bit line electrically connected to said drain region; and
a source line electrically connected to said source region,
wherein in a section along said word line, a length of a boundary between the central portion of said body region said second insulating film is smaller than a length of a boundary between said body region and said first insulating film;
wherein the central portion of the body region on which said second insulating film is formed is completely depleted because a thickness of the central portion is smaller than a width of a maximum depletion layer formed when a predetermined potential is applied to said gate electrode.
11. A device according to claim 10 , wherein said floating body cell has a first data state in which majority carriers are accumulated in said body region, and a second data state in which the majority carriers accumulated in said body region are emitted.
12. A device according to claim 10 , wherein said body region consists of a central portion and a pair of end portions, a top surface of the central portion being covered with a second insulating film on which a gate electrode is formed, said central portion and said pair of end portions being formed along said word line direction.
13. A device according to claim 10 , wherein a bottom surface of said element isolation insulating film is in contact with said first insulating film.
14. A device according to claim 12 , wherein said end portions of said body region are not completely depleted.