IP Library Granted Patent US 7,199,684
Granted Patent B2
US 7,199,684 · App. 11/045,500 · Granted Apr 3, 2007

Filter circuit with a filter stage and balun on a single substrate

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Quick Facts
Patent No.
US 7,199,684
App. No.
11/045,500
Granted
Apr 3, 2007
Kind
B2
Abstract

A filter circuit comprises a balanced port, an unbalanced port and a substrate. A series circuit of a filter stage and a balun is disposed between the balanced port and the unbalanced port. The balun and the filter stage are formed on the substrate.

Claims (31)

1. A filter circuit, comprising:

a balanced port;

an unbalanced port;

a substrate; and

a series circuit comprising a filter stage and a balun, disposed between the balanced port and the unbalanced port,

wherein the filter stage is a balanced filter stage connected to the balanced port and wherein the series circuit further comprises an unbalanced filter stage connected to the unbalanced port, wherein the balun is connected between the balanced filter stage and the unbalanced filter stage and

wherein the balanced filter stage, the unbalanced filter stage, and the balun are formed on the substrate.

2. The filter circuit according to claim 1 , wherein at least one of the filter stages comprises at least one series BAW resonator and at least one parallel BAW resonator.

3. The filter circuit according to claim 1 , wherein the series circuit further comprises at least one adaption element connected between the unbalanced filter stage and the unbalanced port or between the balanced filter stage and the balanced port, wherein the at least one adaption element is formed on the substrate.

4. The filter circuit according to claim 1 , wherein the balun is a transformer element with two coils, wherein the coils are formed on the substrate.

5. The filter circuit according to claim 4 , wherein the coils have a winding ratio to effect an impedance transformation between the unbalanced port and the balanced port.

6. The filter circuit according to claim 4 , wherein the substrate has a high resistance and wherein the coils are formed on the substrate by metal traces.

7. The filter circuit according to claim 6 , wherein the metal traces of the coils are formed with a thickness between 800 nm and 1 μm.

8. The filter circuit according to claim 4 , wherein at least one of the filter stages comprises at least one BAW resonator, and wherein the substrate has an acoustic reflector and the at least one BAW resonator and the coils are formed above the acoustic reflector.

9. The filter circuit according to claim 1 , wherein the substrate comprises at least part of a chip.

10. A filter circuit, comprising:

a balanced port;

an unbalanced port;

a substrate; and

a series circuit comprising a filter stage and a balun, the series circuit disposed between the balanced port and the unbalanced port, wherein the balun and the filter stage are formed on the substrate.

wherein the balun is a transformer element with two coils, wherein the coils are formed on the substrate, and

wherein the substrate has a high resistance and wherein the coils are formed on the substrate by metal traces.

11. The filter circuit according to claim 10 , wherein the coils have a winding ratio to effect an impedance transformation between the unbalanced port and the balanced port.

12. A filter circuit, comprising:

a balanced port;

an unbalanced port;

a substrate; and

a series circuit comprising a filter stage and a balun, the series circuit disposed between the balanced port and the unbalanced port, wherein the balun and the filter stage are formed on the substrate;

wherein the balun is a transformer element with two coils, wherein the coils are formed on the substrate; and

wherein the filter stage comprises at least one BAW resonator, and wherein the substrate has an acoustic reflector and the at least one BAW resonator and the coils are formed above the acoustic reflector.

13. The filter circuit according to claim 12 , wherein the coils are formed by metal traces having thickness between 800 nm and 10 μm.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0703 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2008
From: INFINEON TECHNOLOGIES AG
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 021580/0564 →