CMOS reference voltage circuit
View Patent ↗A CMOS reference voltage circuit, preferably formed on a semiconductor integrated circuit, and outputting a reference voltage having a temperature-independent characteristic, comprises first and second diode-connected transistors (or diodes), respectively grounded and driven with two constant currents bearing a constant current ratio to each other, and a unit for amplifying a differential voltage of output voltages from the first and second transistors by a preset factor and for summing the amplified differential voltage to an output voltage of the first or second transistor.
1. A CMOS reference voltage circuit for generating and outputting a reference voltage, comprising:
a single diode-connected transistor, having an emitter grounded and being driven with a constant current; and
an operational amplifier directly connected to the collector of said diode-connected transistor, said operational amplifier being arranged in a voltage follower type configuration and having an input offset, wherein said offset has a temperature characteristic that counteracts a temperature characteristic of the diode-connected transistor;
wherein said reference voltage is output from an output terminal of said operational amplifier.
2. A CMOS reference voltage circuit for generating and outputting a reference voltage, comprising:
a diode-connected transistor, having an emitter grounded and being driven with a constant current; and
an operational amplifier for receiving an output voltage of said diode-connected transistor, said operational amplifier being arranged in a voltage follower type configuration and having an input offset;
said reference voltage being output from an output terminal of said operational amplifier, and
wherein said operational amplifier is driven with a second constant current;
a gate W/L ratio of two transistors constituting an input differential pair of said operational amplifier is 1:K 2 , K 2 being an integer larger than 1;
a gate W/L ratio of two transistors constituting an active load operating as a load to the two transistors of said input differential pair is K 3 :1, K 3 being an integer larger than 1; and
said offset of said operational amplifier is summed to said output voltage of said diode-connected transistor to produce said reference voltage.
3. A CMOS reference voltage circuit for generating and outputting a reference voltage, comprising:
a diode-connected transistor, having an emitter grounded and being driven with a constant current; and
an operational amplifier for receiving an output voltage of said diode-connected transistor, said operational amplifier being arranged in a voltage follower type configuration and having an input offset;
said reference voltage being output from an output terminal of said operational amplifier, and
wherein said operational amplifier is driven with a second constant current;
a gate W/L ratio of two transistors constituting an input differential pair is K 2 :1, K 2 being an integer larger than 1;
a gate W/L ratio of two transistors constituting an active load operating as a load to the two transistors of the input differential pair is 1:K 3 , K 3 being an integer larger than 1; and
said offset of said operational amplifier is subtracted from said output voltage of said diode-connected transistor to produce said reference voltage.
4. A reference voltage circuit including a differential amplifier circuit, said differential amplifier circuit comprising:
a differential pair comprised of first and second MOS transistors, having sources connected in common and driven with a constant current; and
a first current mirror circuit comprised of third and fourth MOS transistors, connected to drains of the first and second MOS transistors of said differential pair, said third and fourth MOS transistors acting as active loads, wherein
a gate W/L ratio of each of said first and second MOS transistors is 1:K 2 , with K 2 being an integer larger than 1,
a gate W/L ratio of each of said third and fourth MOS transistors is K 3 :1, with K 3 being an integer larger than 1; or
the gate W/L ratio of said first and second MOS transistors is K 2 :1, with the gate W/L ratio of said third and fourth MOS transistors being 1:K 3 ; and
there is provided a bipolar transistor, having an emitter grounded and having a base and a collector connected together with the collector fed with a second constant current; the collector of said bipolar transistor being connected to a gate of said first MOS transistor, a drain and a gate of the second MOS transistor being connected together, a reference voltage being taken out from the drain of said second MOS transistor as an output terminal.
5. The reference voltage circuit as defined in claim 4 comprising:
a fifth MOS transistor having a source grounded, a drain connected to one end of a resistor and having a gate coupled to the other end of said resistor;
a sixth MOS transistor having a source grounded and having a gate connected to the drain of said fifth MOS transistor; and
a second current mirror circuit having an input end and a plurality of output ends, said input end being connected to a drain of said sixth MOS transistor and having said output ends connected to the common source of said first and second MOS transistors of said differential pair and to the collector of said bipolar transistor.
6. A reference voltage circuit including a differential amplifier circuit, said differential amplifier circuit comprising:
a differential pair comprised of first and second MOS transistors, having sources connected in common and driven with a constant current;
a first current mirror circuit comprised of third and fourth MOS transistors, connected respectively to drains of the first and second MOS transistors of said differential pair, said third and fourth MOS transistors acting as active load; and
a fifth MOS transistor arranged in a voltage follower configuration, having a gate connected to the drain of the second MOS transistor and driven with a second constant current, wherein
a gate W/L ratio of said first and second MOS transistors is 1:K 2 , where K 2 being an integer larger than 1, with a gate W/L ratio of said third and fourth MOS transistors being K 3 :1, where K 3 being an integer larger than 1; or
the gate W/L ratio of said first and second MOS transistors is K 2 :1, with the gate W/L ratio of said third and fourth MOS transistors being 1:K 3 ;
a drain of said fifth MOS transistor is an output terminal; said output terminal being connected to a gate of said second MOS transistor of said differential pair to form a voltage follower; and
there being provided a bipolar transistor, having an emitter grounded and having a base and a collector connected together, with the collector being driven with a third constant current;
the collector of said bipolar transistor being connected to a gate of said first MOS transistor of said differential pair;
a reference voltage being taken out at said output terminal.
7. The reference voltage circuit as defined in claim 6 comprising:
a sixth MOS transistor having a source grounded, a drain connected to one end of a resistor and having a gate connected to the other end of said resistor;
a seventh MOS transistor having a source grounded and having a gate connected to the drain of said sixth MOS transistor; and
a second current mirror circuit including an input end and an output end, having the input end connected to a drain of the seventh MOS transistor and having the output end connected to the drain of said sixth MOS transistor, the drain of said fifth MOS transistor, the common source of the first and second MOS transistors of said differential pair and to the collector of said bipolar transistor.