MOS type variable capacitance device
View Patent ↗An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode. A MOS type variable capacitance device capable of obtaining a characteristic of good linearity for a wide range relative to the inter-terminal voltage VT and capable of coping with the improvement of the performance of a VCO circuit, etc., as well as simple in the structure, and capable of being manufactured easily with no requirement for addition of masks and steps can be provided.
1. A MOS type variable capacitance device, comprising:
at least one first semiconductor layer constituted with a first conduction type;
at least one second semiconductor layer in adjacent to the first semiconductor layer at the surface of a semiconductor substrate and constituted with a second conduction type that is different from the first conduction type;
at least one first gate insulating layer disposed on the first semiconductor layer;
at least one second gate insulating layer disposed on the second semiconductor layer;
at least one gate layer arranged on the first gate insulating layer and the second gate insulating layer; and
at least one first conduction type or at least one second conduction type source layer which is arranged adjacent to the first and second gate insulating layers, wherein
the impurity concentration of the first or second semiconductor layer is lower than the impurity concentration of a source layer of an identical conduction type;
when a number of the at least one gate layer is two or more, two of the gate layers are connected to each other;
when a number of the at least one first conduction type or at least one second conduction type source layer is two or more, two of the first conduction type or the second conduction type source layers are connected to each other; and
the gate layer and the source layer are used as electrodes.
2. The MOS type variable capacitance device according to claim 1 , wherein the first semiconductor layer is the semiconductor substrate and the second semiconductor layer is formed selectively in the direction of the depth from the surface of the semiconductor substrate.
3. The MOS type variable capacitance device according to claim 1 , wherein
the first semiconductor layer is formed selectively in the direction of the depth from the surface of the semiconductor substrate, and
the second semiconductor layer is formed selectively in the first semiconductor layer in the direction of the depth from the surface of the first semiconductor layer.
4. The MOS type variable capacitance device according to claim 1 , wherein
the first and the second semiconductor layers are formed selectively in the direction of the depth from the surface of the semiconductor substrate.
5. The MOS type variable capacitance device according to claim 1 , wherein
the region just below at least either one of the first or second gate insulating layer has an impurity concentration different from the impurity concentration in a bulk region of at least one of the first and the second semiconductor layers.
6. The MOS type variable capacitance device according to claim 1 , wherein
the first conduction type or second conduction type source layer contains a first common source layer disposed between the first gate insulating layer and the second gate insulating layer adjacent to each other, and
the first common source layer is extended over the first and second semiconductor layers.
7. The MOS type variable capacitance device according to claim 1 , wherein
the first or second gate insulating layer includes an extended gate insulating layer arranged beyond the boundary between the first semiconductor layer and the second semiconductor layer, and
the first conduction type or second conduction type source layer adjacent to the extended gate insulating layer contains an extended source layer arranged beyond the boundary between the first semiconductor layer and the second semiconductor layer,
the first conduction type or second conduction type source layer adjacent between the first and second gate insulating layers contains a second common source layer arranged beyond the boundary between the first and the second semiconductor layers.
8. A MOS type variable capacitance device constituted with a synthesis capacitance of:
a first MOS type variable capacitance device; and
a second MOS type variable capacitance device with a variable capacitance characteristic that is different than the variable capacitance characteristic of the first MOS type device and having a linearity for a capacitance change region for a wider voltage range applied between the terminals than that of the first MOS type variable capacitance device, wherein
the second MOS type variable capacitance device comprises a back gate layer constituted with a semiconductor layer of conduction type identical with that of a source layer and a drain layer.