Serializer clock synthesizer
View Patent ↗A clock synthesizer uses a serializer to convert a parallel data stream into clock signals. The frequency of the synthesized clock is dependent on the bit values of the parallel data stream and the frequency of the reference clock used by the serializer. Rapid tuning of the frequency is provided by changing the bit values of the parallel data stream. Fine tuning of the frequency is provided by changing the frequency of the reference clock. With this configuration, the clock device is capable of generating clock signals with very low jitter, is tunable to a very fine resolution in frequency, is able to skew to an external trigger with no glitches, and is able to hop to different frequencies with minimal delays. Moreover, the clock device can be designed at fairly low cost, because the serializer is widely available as a component in telecommunications applications.
1. A clock synthesizer comprising:
a serializer circuit having a parallel data input, a reference clock input and a serial data output, the serializer circuit being configured to generate serial data representing a synthesized clock signal through the serial data output based on parallel data received through the parallel data input;
a variable clock generating circuit coupled to the reference clock input of the serializer circuit; and
a device coupled to the parallel data input of the serializer circuit, the device being programmed to generate the parallel data to be supplied to the parallel data input of the serializer circuit;
wherein the serializer circuit further includes a parallel clock input through which a parallel clock that is used to clock in the parallel data is received and a clock output through which a clock is supplied to the device.
2. The clock synthesizer according to claim 1 , wherein the frequency of the synthesized clock signal changes in accordance with changes in the frequency of the clock generated by the variable clock generating circuit.
3. The clock synthesizer according to claim 2 , wherein the variable clock generating circuit comprises a numerically controlled oscillator that provides control over the changes in the frequency of the clock generated by the variable clock generating circuit.
4. The clock synthesizer according to claim 1 , wherein the device has registers that store control parameters of the clock synthesizer including control parameters that determine bit values of the parallel data to be supplied to the parallel data input of the serializer circuit.
5. The clock synthesizer according to claim 4 , wherein the control parameters further include control parameters that determine the frequency of the clock generated by the variable clock generating circuit.
6. The clock synthesizer according to claim 1 , wherein the parallel clock is derived from the clock supplied to the device.