Synchronization primitives for flexible scheduling of functional unit operations

1. A processor, comprising:

a plurality of functional units, each configured to retrieve operations for processing from an operation storage, wherein each of said plurality of functional units is configured to process retrieved operations independently of each other one of said plurality of functional units; and

instruction fetch logic configured to issue instructions for execution by the processor, wherein a subset of said instructions are executable to store operations for processing by said functional units into said operation storage, and wherein a given one of said subset of said instructions is executable on different occasions to store different types of said operations into said operation storage;

wherein said instructions are defined within a programmer-visible instruction set architecture (ISA), and wherein said operations are not defined within said ISA;

wherein said functional units are configured to retrieve and process said operations from said operation storage autonomously with respect to said instruction fetch logic and said subset of instructions; and

wherein said operations stored by said subset of said instructions include synchronization operations configured to coordinate processing of other ones of said operations by said plurality of functional units.

2. The processor as recited in claim 1 , wherein said synchronization operations include a suspend operation and a resume operation.

3. The processor as recited in claim 2 , wherein in response to a given one of said plurality of functional units processing a particular suspend operation, said given functional unit is configured to suspend processing until receiving notification that a resume operation corresponding to said particular suspend operation has been processed.

4. The processor as recited in claim 1 , wherein said functional units include a hash functional unit configured to process cryptographic hash operations and a cipher functional unit configured to process cryptographic cipher operations.

5. The processor as recited in claim 1 , further comprising one or more execution units configured to execute said instructions issued by said instruction fetch logic.

6. The processor as recited in claim 5 , wherein said one or more execution units include a load/store unit configured to execute said subset of said instructions.

7. A system, comprising:

the processor as recited in claim 1 ; and

a system memory coupled to said processor, wherein said system memory includes a plurality of addressable locations;

wherein said operation storage includes a respective control word queue corresponding to each of said plurality of functional units, wherein said respective control word queues map to corresponding addressable locations of said system memory.

8. The system as recited in claim 7 , wherein storing a given one of said operations into said operation storage for processing by a given one of said plurality of functional units comprises storing a control word indicative of said given operation into a particular respective control word queue corresponding to said given functional unit.

9. The system as recited in claim 7 , wherein said processor further comprises a cache, and wherein said respective control word queues are configurable to be stored within said cache.

10. A method, comprising:

issuing instructions for execution by a processor, wherein a subset of said instructions are executable to store operations into an operation storage for processing by a plurality of functional units, and wherein a given one of said subset of said instructions is executable on different occasions to store different types of said operations into said operation storage;

said plurality of functional units retrieving said operations for processing from said operation storage, wherein each of said plurality of functional units is configured to process retrieved operations independently of each other one of said plurality of functional units;

wherein said instructions are defined within a programmer-visible instruction set architecture (ISA) and wherein said operations are not defined within said ISA;

wherein said functional units are configured to retrieve and process said operations from said operation storage autonomously with respect to said issuing of said instructions for execution by said processor; and

wherein said operations stored by said subset of said instructions include synchronization operations configured to coordinate processing of other ones of said operations by said plurality of functional units.

11. The method as recited in claim 10 , wherein said synchronization operations include a suspend operation and a resume operation.

12. The method as recited in claim 11 , further comprising:

in response to a given one of said plurality of functional units processing a particular suspend operation, said given functional unit suspending processing until receiving notification that a resume operation corresponding to said particular suspend operation has been processed.

13. The method as recited in claim 10 , wherein said functional units include a hash functional unit configured to process cryptographic hash operations and a cipher functional unit configured to process cryptographic cipher operations.

14. The method as recited in claim 10 , further comprising executing said instructions issued by said instruction fetch logic within one or more execution units.

15. The method as recited in claim 14 , further comprising executing said subset of said instructions within a load/store unit included within said one or more execution units.

16. The method as recited in claim 10 , wherein storing a given one of said operations into said operation storage for processing by a given one of said plurality of functional units comprises storing a control word indicative of said given operation into a respective control word queue corresponding to said given functional unit.

17. The method as recited in claim 16 , wherein said respective control word queue maps to corresponding addressable locations included within a system memory coupled to said processor.

18. A system, comprising:

a system memory; and

a processor coupled to said system memory, wherein said processor includes:

a plurality of functional units, each configured to retrieve operations for processing from an operation storage, wherein each of said plurality of functional units is configured to process retrieved operations independently of each other one of said plurality of functional units; and

instruction fetch logic configured to issue instructions for execution by the processor, wherein a subset of said instructions are executable to store operations for processing by said functional units into said operation storage, and wherein a given one of said subset of said instructions is executable on different occasions to store different types of said operations into said operation storage;

wherein said instructions are defined within a programmer-visible instruction set architecture (ISA), and wherein said operations are not defined within said ISA;

wherein said functional units are configured to retrieve and process said operations from said operation storage autonomously with respect to said instruction fetch logic and said subset of instructions; and

wherein said operations stored by said subset of said instructions include synchronization operations configured to coordinate processing of other ones of said operations by said plurality of functional units.

19. The system as recited in claim 18 , wherein said synchronization operations include a suspend operation and a resume operation.

20. The system as recited in claim 19 , wherein in response to a given one of said plurality of functional units processing a particular suspend operation, said given functional unit is configured to suspend processing until receiving notification that a resume operation corresponding to said particular suspend operation has been processed.

21. The system as recited in claim 18 , wherein said functional units include a hash functional unit configured to process cryptographic hash operations and a cipher functional unit configured to process cryptographic cipher operations.

22. The system as recited in claim 18 , wherein said processor further includes one or more execution units configured to execute said instructions issued by said instruction fetch logic.

23. The system as recited in claim 22 , wherein said one or more execution units include a load/store unit configured to execute said subset of said instructions.