Non-volatile memory element having memory gate and control gate adjacent to each other
View Patent ↗A memory element structured so as to reduce the size and improve reliability such that a memory gate and control gate are adjacent to each other. The side of a memory gate 115 in contact with a control gate 126 is formed by etching back. This side has a circular arc-shaped curve and is convex towards the control gate 126 . By doing this, a short circuit between the electrodes created by the occurrence of a thin film part in an HTO film 108 can be suppressed.
1. A non-volatile memory element comprising:
a semiconductor substrate;
a first impurity diffusion region and a second impurity diffusion region provided on said semiconductor substrate;
a memory gate, with a charge accumulation section, provided on a part of a channel region disposed between said first and second impurity diffusion regions and;
a control gate provided on another part of said channel region adjacent to said memory gate interposed with an insulating film, wherein;
electric potentials of said memory gate and said control gate are controlled independently; and
said memory gate has a curved surface on a side in contact with said control gate, said curved surface being convex towards said control gate, said control gate being provided on said curved surface interposed with said insulating film.
2. The non-volatile memory element as defined in claim 1 wherein said control gate has a cross sectional shape along that a longitudinal direction of said gate becomes narrower towards the top and away from said semiconductor substrate.
3. The non-volatile memory element as defined in claim 1 wherein a side of said control gate opposite to the one adjacent to said memory gate has a curved surface and is convex towards the outside.
4. The non-volatile memory element as defined in claim 1 wherein said control gate is formed by etching back.
5. The non-volatile memory element as defined in claim 1 wherein said memory gate is formed by etching back and said control gate is provided laterally on a side formed by etching back.
6. The non-volatile memory element as defined in claim 1 wherein the height of said control gate is shorter than that of said memory gate.
7. The non-volatile memory element as defined in claim 1 wherein said memory gate comprises a charge accumulation section, a first conductive film containing a first conductivity type impurity provided on said charge accumulation section, and a second conductive film of a first conductivity type provided on said first conductive film and;
said first conductive film has an impurity concentration different from the impurity concentration of said second conductive film.
8. The non-volatile memory element as defined in claim 1 wherein said memory gate has an electrode width not less than 20 nm and not more than 200 nm.
9. The non-volatile memory element as defined in claim 1 wherein said charge accumulation section comprises a silicon nitride layer, and insulating layers are provided above and below said silicon nitride layer sandwiching the silicon nitride layer.
10. The non-volatile memory element as defined in claim 1 wherein said charge accumulation section comprises multiple dot-shaped dielectric materials disposed separated from one another, and insulating layers are provided above and below said dot-shaped dielectric materials sandwiching said dot-shaped dielectric materials.
11. A semiconductor device comprising: a pair of the non-volatile memory elements as defined in claim 1 provided in parallel, wherein said second impurity diffusion region shared by the non-volatile memory elements is located in a region sandwiched by these non-volatile memory elements; and
a conductive material is embedded in an area of said second impurity diffusion region sandwiched by said pair of the non-volatile memory elements.
12. A memory element comprising:
a semiconductor substrate;
a first impurity diffusion region and a second impurity diffusion region provided on said semiconductor substrate;
a memory gate, with a charge accumulation section, provided on a part of a channel region disposed between said first and second impurity diffusion regions and;
a control gate provided on another part of said channel region adjacent to said memory gate interposed with an insulating film, wherein;
electric potentials of said memory gate and said control gate are controlled independently;
said memory gate has a curved surface on a side in contact with said control gate, said curved surface being convex towards said control gate, said control gate being provided on said curved surface interposed with said insulating film,
said control gate having a cross sectional shape along that a longitudinal direction of said gate becomes narrower towards the top and away from said semiconductor substrate.
13. The memory element as defined in claim 12 wherein a side of said control gate opposite to the one adjacent to said memory gate has a curved surface and is convex towards the outside.
14. The memory element as defined in claim 13 wherein said control gate is formed by etching back.
15. The memory element as defined in claim 14 wherein said memory gate is formed by etching back and said control gate is provided laterally on a side formed by etching back.
16. The memory element as defined in claim 15 wherein the height of said control gate is shorter than that of said memory gate.
17. The memory element as defined in claim 12 wherein said memory gate comprises a charge accumulation section, a first conductive film containing a first conductivity type impurity provided on said charge accumulation section, and a second conductive film of a first conductivity type provided on said first conductive film and;
said first conductive film has an impurity concentration different from the impurity concentration of said second conductive film.
18. The memory element as defined in claim 12 wherein said charge accumulation section comprises multiple dot-shaped dielectric materials disposed separated from one another, and insulating layers are provided above and below said dot-shaped dielectric materials sandwiching said dot-shaped dielectric materials.