Data processing system and method for efficient communication utilizing an in coherency state
View Patent ↗A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
1. A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said method comprising:
in a first cache memory within said first coherency domain of said data processing system, holding a memory block in a storage location associated with an address tag and a coherency state field, wherein said memory block is concurrently cacheable in both the first and second coherency domains; and
indicating by a state of said coherency state field that said address tag is valid, that said storage location does not contain valid data, and that said memory block is likely cached only within said first coherency domain.
2. The method of claim 1 , and further comprising setting said coherency state field to said state in response to an exclusive access request by a second cache memory in said first coherency domain of said data processing system.
3. The method of claim 2 , wherein said exclusive access request comprises a Data Claim (DClaim) operation.
4. The method of claim 2 , wherein:
said exclusive access request comprises a read-with-intent-to-modify (RWITM) operation; and
said method further comprises said first cache memory sourcing said memory block to said second cache memory in said first coherency domain in response to said RWITM operation.
5. The method of claim 2 , wherein said setting comprises setting said coherency state field to said state without first casting out said memory block to a system memory assigned an address associated with said memory block.
6. The method of claim 2 , wherein said state comprises a first state and said setting comprises updating said coherency state field to said first state from a second state indicating that said memory block is valid and modified with respect to a corresponding memory block within a system memory.
7. The method of claim 1 , wherein said setting comprises setting said coherency state field to said state only if a system memory assigned an address associated with said memory block is within said first coherency domain.
8. The method of claim 1 , and further comprising:
in response to a master associated with said first cache memory requesting access to said memory block while said coherency state field is set to the state, accessing said coherency state field of said first cache memory;
in response to said access to said coherency state field indicating said coherency state field is set to said state, transmitting a broadcast operation specifying said access to said memory block, wherein a scope of transmission of the broadcast operation is limited to said first coherency domain.