Patent Assignment
Reel/Frame 027991/0435
Assignment of Assignor's Interest
Recorded: 2012-04-04
Pages: 19
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2012-03-27
Assignee
FACEBOOK, INC.
1601 WILLOW ROAD, MENLO PARK, CALIFORNIA, 94025
Covered Properties
(51)
System and Method for Flexible Multiple Protocols
System and Method for Tracking Changes in L1 Data Cache Directory
System and Method for Generating Effective Address
Method for Providing Multiple Reads/Writes Using a 2READ/2WRITE Register Array
Method to Optimize Effective Page Number to Real Page Number Translation Path from Page Table Entries Match Resumption of Execution Stream
Cache Mechanism and Method for Avoiding Cast Out on Bad Victim Select and Recycling Victim Select Operation
Data Processing System and Method for Handling Castout Collisions
L2 Cache Array Topology for Large Cache with Different Latency Domains
Intelligent Smt Thread Hang Detect Taking into Account Shared Resource Contention/Blocking
Data Processing System and Method for Efficient Communication Utilizing an in Coherency State
Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch
Dynamic Recalculation of Resource Vector at Issue Queue for Steering of Dependent Instructions
Reducing Number of Rejected Snoop Requests by Extending Time to Respond to Snoop Request
Method for Improved Synthesis of Binary Decision Diagrams with Inverted Edges and Quantifiable as Well as Nonquantifiable Variables
System and Method for Text Based Placement Engine for Custom Circuit Design
Apparatus and Method for Using a Single Bank of Efuses to Successively Store Testing Data from Multiple Stages of Testing
Efficient System Bootstrap Loading
Method, Apparatus, and Computer Program Product for a Cache Coherency Protocol State That Predicts Locations of Shared Memory Blocks
Memory Controller Capable of Locating an Open Command Cycle to Issue a Precharge Packet
Queue Design Supporting Dependency Checking and Issue for Simd Instructions Within a General Purpose Processor
Adaptive Sampling of a Static Data Set
Adaptive span computation when ray casting
Dynamic Power Management in a Processor Design
Method, Apparatus, and Computer Program Product for Routing Packets Utilizing a Unique Identifier, Included Within a Standard Address, That Identifies the Destination Host Computer System
Data Processing System and Method for Handling Castout Collisions
System and Method for Flexible Multiple Protocols
L2 Cache Array Topology for Large Cache with Different Latency Domains
Adaptive Sampling of a Static Data Set
Cache Mechanism and Method for Avoiding Cast Out on Bad Victim Select and Recycling Victim Select Operation
Method for Improved Synthesis of Binary Decision Diagrams with Inverted Edges and Quantifiable as Well as Nonquantifiable Variables
Method for Improved Synthesis of Binary Decision Diagrams with Inverted Edges and Quantifiable as Well as Nonquantifiable Variables
Data Processing System and Method for Efficient L3 Cache Directory Management
Data Processing System and Method for Efficient L3 Cache Directory Management
Using a Single Bank of Efuses to Successively Store Testing Data from Multiple Stages of Testing
Queue Design System Supporting Dependency Checking and Issue for Simd Instructions Within a General Purpose Processor
Method to Optimize Effective Page Number to Real Page Number Translation Path from Page Table Entries Match Resumption of Execution Stream
System and Method for Text Based Placement Engine for Custom Circuit Design
Dynamic Recalculation of Resource Vector at Issue Queue for Steering of Dependent Instructions
Intelligent Smt Thread Hang Detect Taking into Account Shared Resource Contention/Blocking
Adaptive Span Computation During Ray Casting
System for Generating Effective Address
Data Processing System and Method for Efficient Communication Utilizing an in Coherency State
Method, Apparatus, and Computer Program Product for a Cache Coherency Protocol State That Predicts Locations of Shared Memory Blocks
Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch
Method, Apparatus, and Computer Program Product for Routing Packets Utilizing a Unique Identifier, Included Within a Standard Address, That Identifies the Destination Host Computer System
Reducing Number of Rejected Snoop Requests by Extending Time to Respond to Snoop Request
Efficient System Bootstrap Loading
Implementing Container Managed Batch Jobs in an Enterprise Java Bean Environment
Dynamic Power Management in a Processor Design
System and Method for Tracking Changes in L1 Data Cache Directory
Apparatus and Method for Providing Multiple Reads/Writes Using a 2READ/2WRITE Register File Array
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.