System for generating effective address
View Patent ↗Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
1. A system for generating an effective address, comprising:
a dispatch unit for dispatching an instruction;
an adder for generating a first portion of the effective address for the instruction by calculating a first plurality of effective address bits of the effective address;
a multiplexer for generating a second portion of the effective address for the instruction by guessing a second plurality of effective address bits of the effective address to form a guessed generated effective address for the instruction;
a mechanism for sending the guessed generated effective address to a translation unit;
a mechanism for determining whether the guessed generated effective address is correct;
responsive to determining that the guessed generated effective address is not correct;
a mechanism for invoking a reject for all load and store instructions;
a mechanism for instructing the translation unit to ignore the guessed generated effective address;
a mechanism for redispatching the instruction for which the guessed generated effective address was not correct;
a mechanism for generating a calculated effective address for the instruction by
calculating all effective address bits of the effective address to form a calculated generated effective address;
scratch registers for storing the calculated generated effective address; and
a mechanism for sending the generated calculated effective address from the scratch registers to the translation unit.
2. The system according to claim 1 , wherein the effective address comprises sixty-four effective address bits, and wherein the first plurality of effective address bits comprises twenty-four bits, and wherein the second plurality of effective address bits comprises forty bits.
3. The system according to claim 1 , wherein the system comprises a content addressable memory (CAM)-based effective address translation design in a multi-threaded environment.
4. A computer program product in a recordable-type computer readable medium for generating an effective address, comprising:
first instructions for dispatching an instruction;
second instructions for generating a first portion of the effective address for the instruction by calculating a first plurality of effective address bits of the effective address using an adder;
third instructions for generating a second portion of the effective address for the instruction by guessing a second plurality of effective address bits of the effective address using a multiplexer to form a guessed generated effective address for the instruction;
fourth instructions for sending the guessed generated effective address to a translation unit;
fifth instructions for determining whether the guessed generated effective address is correct;
responsive to determining that the guessed generated effective address is not correct;
sixth instructions for invoking a reject for all load and store instructions;
seventh instructions for instructing the translation unit to ignore the guessed generated effective address;
eighth instructions for redispatching the instruction for which the guessed generated effective address was not correct;
ninth instructions for generating a calculated effective address for the instruction by calculating all effective address bits of the effective address to form a calculated generated effective address;
tenth instructions for storing the calculated generated effective address in scratch registers; and
eleventh instructions for sending the generated calculated effective address from the scratch registers to the translation unit.
5. The computer program product according to claim 4 , wherein the effective address comprises sixty-four effective address bits, and wherein the first plurality of effective address bits comprises twenty-four bits, and wherein the second plurality of effective address bits comprises forty bits.