Memory controller capable of locating an open command cycle to issue a precharge packet
View Patent ↗A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.
1. A method for a memory controller to locate an open command cycle for issuing a precharge packet when no other packet is currently occupying a bus, said method comprising:
in response to a receipt of two request packets concurrently, determining whether both of said request packets includes a Precharge command, and determining whether one of said request packets includes a non-precharge command and the other one of said request packets includes a Precharge command;
in a determination that both of said request packets includes a Precharge command,
altering at least one command field within one of said request packets; and
merging and sending said merged request packet to said input/output cell; and
in a determination that one of said request packets includes a non-precharge command and the other one of said request packets includes a Precharge command,
immediately sending said request packet having a non-precharge command to an input/output cell;
delaying said request packet having a Precharge command for one command cycle; and
changing dynamic offset of said Precharge command.
2. The method of claim 1 , wherein said method further includes
determining whether one of said request packets includes a Precharge command and the other one of said request packets includes a Refresh Precharge command; and
in a determination that one of said request packets includes a Precharge command and the other one of said request packets includes a Refresh Precharge command, merging and sending said merged request packet to said input/output cell.
3. The method of claim 1 , wherein said non-precharge command is an Act or Col command.
4. The method of claim 1 , wherein said Precharge command is a Precharge+3 command, a Precharge+2 command, or a Precharge+1 command.
5. The method of claim 1 , wherein said memory controller is for controlling extreme data rate (XDR) memories.