Data processing system and method for efficient L3 cache directory management
View Patent ↗A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
1. A cache coherent data processing system, comprising:
a plurality of processing units each having at least an associated upper cache memory;
a lower cache memory associated with the plurality of processing units, wherein the lower cache memory includes:
a plurality of storage locations for storing a memory block of data, wherein each of the plurality of storage locations is sized to store a sub-block of data;
metadata storage for storing metadata describing the memory block; and
a memory controller that is coupled to and controls access to the lower cache memory, wherein the memory controller overwrites at least a portion of metadata in the metadata storage associated with a particular sub-block of data with a coherency state determined as a function of: (1) first coherency metadata related to the particular sub-block of data indicated in the metadata storage, and (2) second coherency metadata related to the particular sub-block of data indicated in the upper cache memory, wherein the memory controller determines a relative priority of the first coherency metadata and the second coherency metadata, wherein the relative priority between coherency metadata is defined as: (Mx|Tx)<<Ig<<Sl<<S<<In<<I, wherein all coherency metadata to the left of a coherency metadata has priority over that coherency metadata.
2. The system of claim 1 , wherein the memory controller overwrites in response to a request to store the particular sub-block of data from an upper cache memory.
3. The system of claim 1 , wherein the memory controller overwrites the portion as a function of the first coherency metadata related to the particular sub-block of data indicated in the metadata storage only if such first coherency metadata is contained in the metadata storage.
4. The system of claim 1 , wherein the memory controller is capable of accessing a coherency state table indicating the coherency state.
5. The system of claim 1 , wherein the coherency state is equal to the second coherency metadata when the second coherency metadata indicates the particular sub-block of data is modified.
6. The system of claim 1 , wherein the coherency state is equal to the first coherency metadata when the first coherency metadata indicates the particular sub-block of data is modified in the lower cache memory.
7. The system of claim 1 , wherein the coherency state is equal to the second coherency metadata when the second coherency metadata indicates the particular sub-block of data is shared and the first coherency metadata does not indicate the particular sub-block of data is modified in the lower cache memory.
8. The system of claim 1 , wherein the memory controller stores the particular sub-block of data in a storage location of the lower cache memory only when the second coherency metadata indicates the particular sub-block of data is modified.