Method and apparatus for semiconductor device and semiconductor memory device

1. A semiconductor device, comprising:

a first conductive region;

a dielectric region;

a second conductive region disposed adjacent to and insulated from the first conductive region by the dielectric region;

a third region disposed adjacent to and insulated from the second conductive region; and

a strain source providing a mechanical stress to at least one of the first and the second conductive regions.

2. The device of claim 1 , wherein the dielectric region includes:

a charge injection filter disposed in between the first and the second conductive regions, wherein the charge injection filter permits transporting of charge carriers of one polarity type from the first conductive region through the second conductive region to the third region and blocks transporting of charge carriers of an opposite polarity type from the second conductive region to the first conductive region.

3. The device of claim 1 , wherein the mechanical stress is a tensile stress or a compressive stress.

4. The device of claim 1 , wherein the mechanical stress produces a strain along a direction substantially parallel to a direction of charge carriers transport in the second conductive region.

5. The device of claim 1 , wherein the second conductive region comprises material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, silicide, n+ polysilicon, p+ polysilicon, n+ poly SiGe, porous silicon, and p+ poly SiGe.

6. The device of claim 1 , wherein the strain source comprises material selected from the group consisting of nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

7. The device of claim 1 , wherein the strain source comprises dislocation loops in at least one of the first and the second conductive regions.

8. The device of claim 2 , wherein the charge injection filter comprises:

a first dielectric disposed adjacent to the second conductive region; and

a second dielectric disposed adjacent to the first conductive region, wherein the first dielectric has an energy band gap narrower than an energy band gap of the second dielectric.

9. The device of claim 8 , wherein a product of a dielectric constant of the first dielectric and a thickness of the second dielectric is greater than a product of a dielectric constant of the second dielectric and a thickness of the first dielectric.

10. The device of claim 8 , wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al 2

O 3 , HfO 2 , TiO 2 , ZrO 2 , Ta 2 O 5 , and alloys formed thereof.

11. The device of claim 8 , wherein the second dielectric comprises oxynitride, and the first dielectric comprises material selected from the group consisting of nitride, Al 2 0 3 , HfO 2 , TiO 2 , ZrO 2 , Ta 2 O 5 , HfO 2 —SiO 2 , and alloys formed thereof.

12. The device of claim 1 , wherein the third region comprises material selected from the group consisting of conductive material, nano-particles, and dielectrics.

13. The device of claim 1 , wherein the mechanical stress has a magnitude of stress level in the range of about 60 MPa to about 2 GPa.

14. The device of claim 1 , wherein the mechanical stress is controlled by ion implantation.

15. The device of claim 14 , wherein the ion implantation comprises implanting a chemical element selected from the group consisting of Ge, Si, As, and nitrogen.

16. A semiconductor device comprising,

a first conductive region having charge carriers for ballistic transport;

a second conductive region disposed adjacent to and insulated from the first conductive region to control the ballistic transport of the charge carriers;

a third region disposed adjacent to and insulated from the second conductive region, the third region for receiving the charge carriers with an injection efficiency for the ballistic transport; and

a strain source for generating mechanical stress in at least one of the first and second conductive regions to enhance the injection efficiency of the ballistic transport.

17. The device of claim 16 , wherein the strain source comprises a strain material contacting at least one of the first and second conductive regions.

18. The device of claim 16 , wherein the strain source comprises dislocation loops in at least one of the first and second conductive regions.

19. A semiconductor device comprising,

a first conductive region having a population of charge carriers;

a second conductive region disposed adjacent to and insulated from the first conductive region for controlling tranport of charge carriers from the first conductive region, the charge carriers in the second conductive region having a mean-free-path;

a third region disposed adjacent to and insulated from the second conductive region, the third region for receiving the charge carriers with an injection efficiency;

a strain source providing a mechanical stress in at least one of the first and second conductive regions to alter the injection efficiency.

20. The device of claim 19 , wherein the population of charge carriers in the first conductive region is altered by the mechanical stress to enhance the injection efficiency.

21. The device of claim 19 , wherein the mean-free-path in the second conductive region is increased by the mechanical stress to enhance the injection efficiency.