CMOS image device with polysilicon contact studs

1. A CMOS image device comprising:

a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region;

a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of transistors having junction regions;

first contact studs formed on the floating diffusion region and the junction region in the pixel array region; and

second contact studs formed on the junction regions in the CMOS logic region,

wherein the first contact studs comprise a different material from at least one of the second contact studs.

2. The CMOS image device of claim 1 , wherein the first contact studs comprise impurity-doped polysilicon layers.

3. The CMOS image device of claim 1 , wherein the at least one of the second contact studs comprises metal.

4. A CMOS image device comprising:

a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region;

a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of nMOS transistors and pMOS transistors;

contact studs formed on the floating diffusion region and the junction region in the pixel array region, the contact studs comprising impurity-doped polysilicon layers; and

a contact stud formed on a junction region of one of the pMOS transistors in the CMOS logic region, the contact stud being formed of a metal.

5. A CMOS image device comprising:

a pixel array region including a photo diode region for sensing light, a transfer transistor for transferring charges generated in the photo diode region, a reset transistor for periodically resetting a floating diffusion region storing transferred charges, and a source follower having at least one MOS transistor for buffering a signal according to charges filled in the floating diffusion region;

a CMOS logic region disposed around the pixel array region, the CMOS logic region including nMOS transistors and pMOS transistors;

first contact studs formed on the floating diffusion region, a junction region of the transfer transistor, a junction region of the reset transistor, and a junction region of the MOS transistor of the source follower in the pixel array region, wherein the first contact studs are formed of a doped polysilicon layer; and

second contact studs formed on a junction region of the nMOS transistor and a junction region of the pMOS transistor in the CMOS logic region, wherein the second contact studs are formed of a metal.

6. The CMOS image device of claim 5 , wherein the floating diffusion region, the junction region of the transfer transistor, the junction region of the reset transistor, and the junction of the MOS transistor of the source follower comprise low concentration n-type impurity regions.

7. The CMOS image device of claim 5 , wherein the floating diffusion region, the junction region of the transfer transistor, the junction region of the reset transistor, and the junction of the MOS transistor of the source follower are formed in a type of lightly doped drain including low concentration n-type impurity regions and high concentration n-type impurity regions.

8. The CMOS image device of claim 5 , further comprising third contact studs on the gate electrode of the reset transistor and the gate electrode of the MOS transistor of the source follower, wherein the third contact studs are formed of a doped-polysilicon layer.

9. The CMOS image device of claim 5 , further comprising third contact studs on the gate electrode of the reset transistor and the gate electrode of the MOS transistor of the source follower, wherein the third contact studs are formed of a metal.

10. The CMOS image device of claim 9 , wherein the third contact studs comprise a barrier metal layer including a titanium/titanium nitride layer and a tungsten metal layer.