Granted Patent B1

US 7,864,816 · App. 11/056,753 · Granted Jan 4, 2011

Assignee: Marvell International Ltd.

Abstract

Claims (163)

1. An integrated circuit comprising:

one or more ports to transmit and receive packets of first data on a network; and

a forwarding engine to transfer the packets of the first data between the ports;

wherein at least one of the ports comprises:

a packet generator to originate a first packet of the first data received by the at least one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data;

a network transmit interface to transmit the first packet of the first data;

a network receive interface to receive a second packet transmitted in reply to the first packet of the first data; and

a controller to calculate a network delay that includes a queue delay that occurs when the first packet is queued for transmission based on the second data representing the time of generation of the first packet of the first data and the second packet.

2. The integrated circuit of claim 1 :

wherein the controller calculates the network delay based on the second data representing the time of generation of the first packet of the first data and a time of receipt of the second packet by the network receive interface.

3. The integrated circuit of claim 1 :

wherein the second packet comprises third data; and

wherein the controller calculates the network delay based on the second data representing the time of generation of the first packet of the first data and the third data in the second packet.

4. The integrated circuit of claim 3 :

wherein the third data in the second packet represents a time of transmission of the second packet.

5. The integrated circuit of claim 3 :

wherein the third data in the second packet represents a time of receipt of the first packet of the first data.

6. The integrated circuit of claim 1 :

wherein the controller

calculates a plurality of the network delays; and

determines a network jitter based on the plurality of the network delays.

7. The integrated circuit of claim 1 , wherein the at least one of the ports further comprises:

an egress queue to store the packets of the first data received by the at least one of the ports from the forwarding engine;

a test queue to store the packets of the first data originated by the packet generator; and

a scheduler comprising

a first input in communication with the egress queue,

a second input in communication with the test queue, and

an output in communication with the network transmit interface.

8. The integrated circuit of claim 1 , wherein the at least one of the ports further comprises:

an ingress queue to store the packets of the first data received by the network receive interface.

9. The integrated circuit of claim 1 , further comprising:

a classifier to determine one or more properties of the packets of the first data received by the network receive interface; and

a counter to count a number of packets of the first data received by the network receive interface that have properties that match one or more property definitions.

10. The integrated circuit of claim 9 , wherein the one or more property definitions comprise at least one of the group consisting of:

a value for a field in the packets of the first data that indicates the packets of the first data were originated by one of the ports in the integrated circuit;

a value for a field in the packets of the first data that indicates the packets of the first data were originated by a port in another integrated circuit; and

one or more qualities of service for the packets of the first data.

11. The integrated circuit of claim 9 , wherein the at least one of the ports:

receives a request for contents of the counter; and

transmits a packet of the first data comprising the contents of the counter.

12. A network switch comprising the integrated circuit of claim 1 .

13. A network device comprising the integrated circuit of claim 1 .

14. The network device of claim 13 , wherein the network device includes one of a wireless access point and a wireless client station.

15. The network device of claim 14 , further comprising:

a user interface to provide one or more property definitions to the integrated circuit, and to retrieve contents of a counter.

16. A method comprising:

transmitting and receiving packets of first data on a network via a plurality of ports of an integrated circuit;

transferring the packets of the first data between the ports;

generating using a packet generator included in one of the ports a first packet of the first data received by the one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data;

transmitting the first packet of the first data;

receiving a second packet transmitted in reply to the first packet of the first data; and

calculating a network delay that includes a queue delay that occurs when the first packet is queued for transmission based on the second data representing the time of generation of the first packet of the first data and the second packet using a controller included in the one of the ports.

17. The method of claim 16 :

wherein the network delay is calculated based on the second data representing the time of generation of the first packet of the first data and a time of receipt of the second packet by the integrated circuit.

18. The method of claim 16 :

wherein the second packet comprises third data; and

wherein the network delay is calculated based on the second data representing the time of generation of the first packet of the first data and the third data in the second packet.

19. The method of claim 18 :

wherein the third data in the second packet represents a time of transmission of the second packet.

20. The method of claim 18 :

wherein the third data in the second packet represents a time of receipt of the first packet of the first data.

21. The method of claim 16 , further comprising:

calculating a plurality of the network delays; and

determining a network jitter based on the plurality of the network delays.

22. The method of claim 16 , further comprising:

determining one or more properties of the received packets of the first data; and

counting a number of packets of the first data received by the network receive interface that have properties that match one or more property definitions.

23. The method of claim 22 , wherein the one or more property definitions comprise at least one of the group consisting of:

a value for a field in the packets of the first data that indicates the packets of the first data were originated by one of the ports in the integrated circuit;

a value for a field in the packets of the first data that indicates the packets of the first data were originated by a port in another integrated circuit; and

one or more qualities of service for the packets of the first data.

24. The method of claim 16 , further comprising:

receiving a request for the number of packets of the first data received by the network receive interface that have properties that match one or more property definitions; and

transmitting a packet of the first data comprising the number of packets of the first data received by the network receive interface that have properties that match the one or more property definitions.

25. An integrated circuit comprising:

one or more ports to transmit and receive packets of first data on a network; and

a host interface to transmit and receive the packets of the first data;

wherein at least one of the ports comprises:

a packet generator to originate a first packet of the first data received by the at least one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data;

a network transmit interface to transmit the first packet of the first data;

a network receive interface to receive a second packet transmitted in reply to the first packet of the first data; and

a controller to calculate a network delay that includes a queue delay that occurs when the first packet is queued for transmission based on the second data representing the time of generation of the first packet of the first data and the second packet.

26. The integrated circuit of claim 25 :

wherein the controller calculates the network delay based on the second data representing the time of generation of the first packet of the first data and a time of receipt of the second packet by the network receive interface.

27. The integrated circuit of claim 25 :

wherein the second packet comprises third data; and

wherein the controller calculates the network delay based on the second data representing the time of generation of the first packet of the first data and the third data in the second packet.

28. The integrated circuit of claim 27 :

wherein the third data in the second packet represents a time of transmission of the second packet.

29. The integrated circuit of claim 27 :

wherein the third data in the second packet represents a time of receipt of the first packet of the first data.

30. The integrated circuit of claim 25 :

wherein the controller

calculates a plurality of the network delays; and

determines a network jitter based on the plurality of the network delays.

31. The integrated circuit of claim 25 , wherein the at least one of the ports further comprises:

an egress queue to store the packets of the first data received by the at least one of the ports from the host interface;

a test queue to store the packets of the first data originated by the packet generator; and

a scheduler comprising

a first input in communication with the egress queue,

a second input in communication with the test queue, and

an output in communication with the network transmit interface.

32. The integrated circuit of claim 25 , wherein the at least one of the ports further comprises:

an ingress queue to store the packets of the first data received by the network receive interface.

33. The integrated circuit of claim 25 :

wherein the at least one of the ports further comprises a network receive interface to receive packets of the first data; and

wherein the integrated circuit further comprises

a classifier to determine one or more properties of the packets of the first data received by the network receive interface, and

a counter to count a number of packets of the first data received by the network receive interface that have properties that match one or more property definitions.

34. The integrated circuit of claim 33 , wherein the one or more property definitions comprise at least one of the group consisting of:

a value for a field in the packets of the first data that indicates the packets of the first data were originated by one of the ports in the integrated circuit;

a value for a field in the packets of the first data that indicates the packets of the first data were originated by a port in another integrated circuit; and

one or more qualities of service for the packets of the first data.

35. The integrated circuit of claim 33 , wherein the at least one of the ports:

receives a request for the contents of the counter; and

transmits a packet of the first data comprising the contents of the counter.

36. A network switch comprising the integrated circuit of claim 25 .

37. A network device comprising the integrated circuit of claim 25 .

38. A network interface controller (NIC) comprising the integrated circuit of claim 25 .

39. The network device of claim 38 , further comprising:

a user interface to provide one or more property definitions to the integrated circuit, and to retrieve contents of a counter.

40. A method comprising:

transmitting and receiving packets of first data on a network via one or more ports of an integrated circuit;

generating using a packet generator included in one of the ports a first packet of the first data received by the one of the ports from the network, wherein the first packet comprises second data representing a time of generation of the first packet of the first data;

transmitting the first packet of the first data;

receiving a second packet transmitted in reply to the first packet of the first data; and

calculating a network delay that includes a queue delay that occurs when the first packet is queued for transmission based on the second data representing the time of generation of the first packet of the first data and the second packet using a controller included in the one of the ports.

41. The method of claim 40 :

wherein the network delay is calculated based on the second data representing the time of generation of the first packet of the first data and a time of receipt of the second packet by the network receive interface.

42. The method of claim 40 :

wherein the second packet comprises third data; and

wherein the network delay is calculated based on the second data representing the time of generation of the first packet of the first data and the third data in the second packet.

43. The method of claim 42 :

wherein the third data in the second packet represents a time of transmission of the second packet.

44. The method of claim 42 :

wherein the third data in the second packet represents a time of receipt of the first packet of the first data.

45. The method of claim 40 , further comprising:

calculating a plurality of the network delays; and

determining a network jitter based on the plurality of the network delays.

46. The method of claim 40 , further comprising:

determining one or more properties of the received packets of the first data, and

counting a number of packets of the first data received by the network receive interface that have properties that match one or more property definitions.

47. The method of claim 46 , wherein the one or more property definitions comprise at least one of the group consisting of:

a value for a field in the packets of the first data that indicates the packets of the first data were originated by one of the ports in the integrated circuit;

a value for a field in the packets of the first data that indicates the packets of the first data were originated by a port in another integrated circuit; and

one or more qualities of service for the packets of the first data.

48. The method of claim 40 , further comprising:

receiving a request for the number of packets of the first data received by the network receive interface that have properties that match one or more property definitions; and

transmitting a packet of the first data comprising the number of packets of the first data received by the network receive interface that have properties that match the one or more property definitions.

49. The integrated circuit of claim 1 :

wherein the controller:

includes in the first packet third data representing a time of transmission when the first packet is transmitted; and

calculates the network delay based on the third data representing the time of transmission of the first packet and a time of receipt of the second packet by the network receive interface.

50. The integrated circuit of claim 25 :

wherein the controller:

includes in the first packet third data representing a time of transmission when the first packet is transmitted; and

calculates the network delay based on the third data representing the time of transmission of the first packet and a time of receipt of the second packet by the network receive interface.

51. The method of claim 16 further comprising:

including in the first packet third data representing a time of transmission when the first packet is transmitted; and

calculating the network delay based on the third data representing the time of transmission of the first packet and a time of receipt of the second packet.

52. The method of claim 40 further comprising:

including in the first packet third data representing a time of transmission when the first packet is transmitted; and

calculating the network delay based on the third data representing the time of transmission of the first packet and a time of receipt of the second packet.

Assignments (8)

Continuity (1)