Clock duty cycle based access timer combined with standard stage clocked output register
View Patent ↗An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.
1. A method of testing a circuit element under test comprising:
generating a clocked test signal;
decreasing the duty cycle of the clocked test signal until the capture register fails to receive the output of the circuit element under test;
capturing an output of the element under test in a capture register at a clock edge through a multiplexer, wherein the element under test catches the clock edge and strobes an output, thereby strobing the multiplexer, said multiplexer comprising;
a strobe on/off latch pair for capturing a TIMER_ON signal, a GLOBAL_CLOCK signal, and a GLOBAL CLOCK B signal, wherein the multiplexer outputs a signal to a DC MODE NAND gate and a signal to an AC MODE NAND gate;
wherein the DC MODE NAND gate receives the GLOBAL CLOCK B signal and a DC MODE signal;
wherein the AC MODE NAND gate receives the GLOBAL CLOCK signal and an AC MODE signal; and
wherein the AC MODE NAND gate and the DC MODE NAND gate outputs being NANDED to an input of a capture register to thereby multiplex the AC mode and the DC mode of the capture register for comparison with a data output of the circuit element under test.
2. The method of claim 1 comprising capturing the delay and duty cycle.
3. The method of claim 1 comprising strobing the circuit element under test on the rising edge of the clocked test signal.
4. The method of claim 1 comprising strobing the circuit element under test on the falling edge of the clocked test signal.
5. The method of claim 1 comprising changing the capture clock strobe timing of the output capture register of the circuit element under test to thereby measure the relative access time of the element under test.
6. A circuit comprising:
an element to be tested and built in test circuitry including;
a clocked output register, a multiplexer, a strobe on/off L1/L2 latch pair and a clock duty cycle based access timer, said access timer receiving a signal from the L1/L2 latch pair;
the access timer comprising two NAND circuits, said NAND circuits receiving timing and mode signals as inputs,
wherein said multiplexer receives a signal from said access timer, from the circuit under test and a capture register, said multiplexer comprising;
a strobe on/off latch pair for capturing a TIMER_ON signal, a GLOBAL_CLOCK signal, and a GLOBAL CLOCK B signal, wherein the multiplexer outputs a signal to a DC MODE NAND gate and a signal to an AC MODE NAND gate;
wherein the DC MODE NAND gate receives the GLOBAL CLOCK B signal and a DC MODE signal;
wherein the AC MODE NAND gate receives the GLOBAL CLOCK signal and an AC MODE signal;
wherein the AC MODE NAND gate and the DC MODE NAND gate outputs being NANDED to an input of a capture register to thereby multiplex the AC mode and the DC mode of the capture register for comparison with a data output of the circuit element under test.
7. The circuit of claim 6 wherein the element to be tested is a SRAM.
8. The circuit of claim 6 wherein the element to be tested is a logic element.