System and method for clock detection with glitch rejection
View Patent ↗A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.
1. A method for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, the method comprising the steps of:
counting a first number M of clock pulses related to the at least one clock signal within a predefined cycle period based on a reference clock signal that is applied to an independent input port of the integrated circuit system; and
comparing the counted first number M of clock pulses with at least one reference number, wherein depending on the result of the comparison the presence of the at least one clock signal is detected or not.
2. A method according to claim 1 , wherein said reference clock signal may be implemented as a non interruptible clock source.
3. A method according to claim 2 , wherein said predefined cycle period is equal to N cycles of the reference clock signal.
4. A method according to claim 3 , wherein said predefined cycle period of N cycles of the reference clock signal is defined by a Linear Feedback Shift Register (LFSR) unit.
5. A method according to claim 1 , wherein said reference number is represented via a minimum value M[min] as a hard coded lower bound or a maximum value M[max] as a hard coded upper bound.
6. A method according to claim 1 , including the step of determining the frequency of the at least one clock signal via the counted first number of clock pulses within the predefined cycle period.
7. A method according to claim 5 , including the step of determining the number N of cycles of the reference clock signal via the following equation:
N/f(xtal)>=M[min]*2/f(clk), wherein
N represents number of cycles of the reference clock signal;
M[min] represents said minimum value M[min];
f(xtal) represents the frequency of the reference clock signal;
f(clk) represents for the frequency of the at least one clock signals.
8. A method according to claim 5 , including the step of determining the number N of cycles of the reference clock signal via the following equation:
N/f(xtal)>M[min]*2/f(clk), wherein
N represents number of cycles of the reference clock signal;
M[min] represents said minimum value M[min];
f(xtal) represents the frequency of the reference clock signal;
f(clk) represents for the frequency of the at least one clock signals.
9. A method according to claim 1 , including resetting the integrated circuit system after N+1 cycles of the reference clock signal.
10. An integrated circuit system for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of said integrated circuit system, the system comprising:
a counter unit for counting a first number of clock pulses related to the at least one clock signal within a predefined cycle period based on a reference clock signal that is applied to an independent input port of the integrated circuit system; and
a comparison unit for comparing the first number of clock pulse with a reference number, wherein depending on the result of the comparison the presence of the at least one clock signal is detected or not.
11. An integrated circuit system according to claim 10 , wherein said counter unit comprises at least a first stage unit, a delay circuit, a finite state machine (FSM) unit, a linear feedback shift register (LFSR) unit, a second comparison unit and a third stage unit.
12. An integrated circuit system according to claim 10 , wherein said comparison unit comprises a first comparison unit and a second stage unit.
13. An integrated circuit system according to claim 11 , wherein said first stage unit comprises at least one Flip-Flop-device and at least one converter unit.
14. An integrated circuit system according to claim 11 , wherein said delay unit consists of at least three Flip-Flop-devices.
15. An integrated circuit system according to claim 11 , wherein said finite state machine (FSM) unit comprises at least one combination logic unit and at least one Flip-Flop-device.
16. An integrated circuit system according to claim 12 , wherein said a second stage unit comprises at least one logic unit and at least one Flip-Flop-device.
17. An integrated circuit system according to claim 12 , wherein the system comprises at least a first and second input port and at least one output port, wherein said at least one clock signal is applied to said first input port, a reference clock signal is applied to said second input port and at least one output signal is dispensed at said output port.
18. An integrated circuit system according to claim 17 , wherein said output signal is set to the logic value “high” if the presence of the at least one clock signal is detected and is set to the logic value “low” if the presence of the at least one clock signal is not detected.