Low redundancy data RAM architecture for monolithic time-space switches

1. A non-blocking time and space switch, comprising a memory core wherein time-slots are sequentially written in a data matrix,

wherein the data matrix is replicated using more than one replica representative, and

wherein a replica representative belongs to a set of matrices, obtained by a column index permutation of the original data matrix, such that a number of common time-slots of any two columns of different matrices of the set is less than a minimum between a number of rows N R and a number of columns N C of the matrices.

2. A non-blocking time and space switch according to claim 1 , wherein any two columns, belonging to any different replica representatives, have no more than one time-slot in common.

3. A non-blocking time and space switch according to claim 1 , wherein the replica representatives are defined by the set of functions

T n ( a jk )≡ a j, (k+n*j)mod(Nc)

n= 0 . . . N T −1 , j= 0 . . . N R −1 , k= 0 . . . N C −1

where a jk is the time slot in the (j, k) position of the data matrix,

N T is the number of replica representatives,

N R is the number of rows of the data matrix,

N C is the number of columns of the data matrix.

4. A non-blocking time and space switch according to claim 2 , wherein the replica representatives are defined by the set of functions

T n ( a jk )≡ a j, (k+n*j)mod(Nc)

n= 0 . . . N T −1 , j= 0 . . . N R −1 , k= 0 . . . N C −1

where a jk is the time slot in the (j, k) position of the data matrix,

N T is the number of replica representatives,

N R is the number of rows of the data matrix,

N C is the number of columns of the data matrix.

5. A non-blocking time and space switch according to claim 3 , wherein the number N T of replica representatives, with indexes {n 0 , . . . n NT−1 }, is limited by

( j*|n′−n ″|)mod( N C )≠0

for any n′, n″ ε {n 0 , . . . n NT−1 }, n′≠n″ and j=1, . . . N R −1

6. A non-blocking time and space switch according to claim 4 , wherein the number N T of replica representatives, with indexes {n 0 , . . . n NT−1 }, is limited by

( j*|n′−n ″|)mod( N C )≠0

for any n′, n″ ε {n 0 , . . . n NT−1 }, n′≠n″ and j=1, . . . N R −1.

7. A non-blocking time and space switch according to claim 1 , wherein the memory core comprises RAMs having two or more ports.

8. A non-blocking time and space switch according to claim 2 , wherein the memory core comprises RAMs having two or more ports.

9. A non-blocking time and space switch according to claim 3 , wherein the memory core comprises RAMs having two or more ports.

10. A non-blocking time and space switch according to claim 4 , wherein the memory core comprises RAMs having two or more ports.

11. A non-blocking time and space switch according to claim 5 , wherein the memory core comprises RAMs having two or more ports.

12. A non-blocking time and space switch according to claim 6 , wherein the memory core comprises RAMs having two or more ports.

13. A non-blocking time and space switch according to claim 1 , wherein the memory core comprises flip-flops and multiplexers.

14. A method for operating a non-blocking time and space switch, wherein time-slots are sequentially written in a data matrix, said method comprising:

replicating the data matrix using more than one replica representative,

wherein the replica representative belongs to a set of matrices, obtained by a column index permutation of the original data matrix, such that a number of common time-slots of any two columns of different matrices of the set is less than a minimum between a number of rows N R and a number of columns N C of the matrices.

15. A method for operating a non-blocking time and space switch according to claim 14 , wherein any two columns, belonging to any different replica representatives, have no more than one time-slot in common.

16. A method for operating a non-blocking time and space switch according to claim 14 , wherein the replica representatives are defined by the set of functions

T n ( a jk )≡ a j, (k+n*j)mod(Nc)

n= 0 . . . N T −1 , j= 0 . . . N R −1 , k= 0 . . . N C −1

where a jk is the time slot in the (j, k) position of the data matrix,

N T is the number of replica representatives,

N R is the number of rows of the data matrix,

N C is the number of columns of the data matrix.

17. A method for operating a non-blocking time and space switch according to claim 15 , wherein the replica representatives are defined by the set of functions

T n ( a jk )≡ a j, (k+n*j)mod(Nc)

n= 0 . . . N T −1 , j= 0 . . . N R −1 , k= 0 . . . N C −1

where a jk is the time slot in the (j, k) position of the data matrix,

N T is the number of replica representatives,

N R is the number of rows of the data matrix,

N C is the number of columns of the data matrix.

18. A method for operating a non-blocking time and space switch according to claim 16 , wherein the number N T of replica representatives, with indexes {n 0 , . . . n NT−1 }, is limited by

( j*|n′−n ″|)mod( N C )≠0

for any n′, n″ ε{n 0 , . . . n NT−1 }, n′≠n″ and j=1, . . . N R −1.

19. A method for operating a non-blocking time and space switch according to claim 17 , wherein the number NT of replica representatives, with indexes {n 0 , . . . n NT−1 }, is limited by

( j*|n′−n ″|)mod( N C )≠0

for any n′, n″ ε {n 0 , . . . n NT−1 }, n′≠n″ and j=1, . . . N R −1.