Copper recess process with application to selective capping and electroless plating
View Patent ↗An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
1. A method for selectively capping metal features of an interconnect structure, wherein said interconnect structure is positioned above at least one layer of logical and functional devices, said method comprising:
recessing said metal features;
depositing a cap lever over said interconnect structure;
planarizing said interconnect structure to form caps only above said metal features; and
before said depositing of said cap layer, depositing a barrier layer above recessed metal features produced by said recessing process.
2. The method in claim 1 , wherein said depositing of said barrier layer comprises electroless plating.
3. The method in claim 1 , wherein said cap layer comprises one of a metal material and a dielectric material.
4. The meted in claim 1 , wherein said interconnection structure includes an upper surface and said depositing and planarizing processes form said caps along said upper surface.
5. The method in claim 1 , wherein said planarizing process stops on mask material positioned adjacent to said conductive features and along an upper surface of said interconnection structure.
6. A method of forming an integrated circuit structure, said method comprising:
forming at least one layer of logical and functional devices;
forming at least one interconnection layer above said layer of logical and functional devices, wherein said forming of said interconnection layer comprises:
forming an insulator layer;
forming metal features in said insulator layers;
recessing said metal features;
depositing a cap layer over said insulator layer;
planarizing said insulator layer to form caps only above said metal features; and,
before said depositing of said cap layer, depositing a barrier layer above recessed metal features produced by said recessing process.
7. The method in claim 6 , wherein said depositing of said barrier layer comprises electroless plating.
8. The method in claim 6 , wherein said cap layer comprises one of a metal material and a dielectric material.
9. The method in claim 6 , wherein said insulator layer includes an upper surface and said depositing and planarizing processes form said caps along said upper surface.
10. The method in claim 6 , wherein said planarizing process stops on mask material positioned adjacent to said conductive features and along an upper surface of said insulator layer.