Frequency synthesizer using PLL architecture for wireless frequency allocation
View Patent ↗An apparatus method to provide a frequency synthesizer using a phase locked loop in a communication device to provide a particular frequency allocation to generate an output from the PLL. The synthesizer includes a phase locked loop (PLL) circuit that has a feedback loop. The feedback loop has a feedback divider circuit that provides an N integer division of an output signal from the PLL in the feedback loop to close loop with the reference signal at a front end of the PLL. A value for feedback factor N to be used in the N integer division is based on a particular channel frequency selected and in which the feedback factor N is selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.
1. An apparatus comprising:
a clock divider circuit to receive a clock signal and to divide the clock signal to generate a reference signal having one of a plurality of reference frequencies, the reference frequencies to be based on a frequency band selected for a communication protocol or protocols; and
a phase locked loop (PLL) circuit having a feedback loop in which a feedback divider circuit provides an N integer division of an output signal from the PLL in the feedback loop to close loop with the reference signal at a front end of the PLL, in which a value for feedback factor N to be used in the N integer division is to be based on a particular channel frequency selected and in which the feedback factor N is to be selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.
2. The apparatus of claim 1 wherein the reference frequencies are based on a frequency band for a 802.11a communication standard.
3. The apparatus of claim 1 wherein the reference frequencies are based on a frequency band for 802.11b and 802.11 g communication standards.
4. The apparatus of claim 1 wherein the reference frequencies are based on frequency bands for 802.11a, 802.11b and 802.11 g communication standards.
5. The apparatus of claim 4 wherein the clock signal is a 20 MHz signal and the reference frequencies are obtained by dividing the 20 MHz signal by factors of 3, 6 and 15 to generate reference frequencies of 6.667 MHz, 3.333 MHz and 1.333 MHz.
6. The apparatus of claim 1 wherein the feedback loop of the PLL does not employ a divide by 2 circuit to divide the output signal by a factor of 2.
7. A synthesizer comprising:
a clock divider circuit to receive a clock signal and to divide the clock signal to generate a reference signal having one of a plurality of reference frequencies, the reference frequencies to be based on a frequency band selected for a communication protocol or protocols;
a phase frequency detector, forming a front end of a phase locked loop (PLL), coupled to receive the reference signal and to generate a signal to control output of the PLL;
a voltage controlled oscillator (VCO), in response to the signal from the phase frequency detector, to generate a VCO signal as the output of the PLL; and
a divide by N circuit, coupled in a feedback loop between the VCO and the phase frequency detector, to receive the output of the PLL and to provide an N integer division of the VCO signal as feedback to the phase frequency detector, in which a value for feedback factor N to be used in the N integer division is to be based on a particular channel frequency selected and in which the feedback factor N is to be selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.
8. The synthesizer of claim 7 wherein the reference frequencies are based on frequency bands for 802.11a, 802.11b and 802.11 g communication standards.
9. The synthesizer of claim 8 wherein the clock signal is a 20 MHz signal and the reference frequencies are obtained by dividing the 20 MHz signal by factors of 3, 6 and 15 to generate reference frequencies of 6.667 MHz, 3.333 MHz and 1.333 MHz.
10. The synthesizer of claim 9 wherein the reference frequency selected is approximately 6.667 MHz and an integer value selected for N is in an approximate range of 492-570 to generate channel frequencies of a lower band of the 802.11a standard.
11. The synthesizer of claim 10 wherein the reference frequency selected is approximately 3.333 MHz and an integer value selected for N is in an approximate range of 1145-1180 to generate channel frequencies of an upper band of the 802.11a standard.
12. The synthesizer of claim 10 wherein the reference frequency selected is approximately 3.333 MHz and an integer value selected for N is in an approximate range of 1145-1165 to generate channel frequencies of one portion of an upper band of the 802.11a standard and wherein the reference frequency selected is approximately 6.667 MHz and an integer value selected for N is in an approximate range of 585-590 to generate channel frequencies of a second portion of the upper band of the 802.11a standard.
13. The synthesizer of claim 9 wherein the reference frequency selected is approximately 1.333 MHz and an integer value selected for N is in an approximate range of 2412-2484 to generate channel frequencies of the 802.11b and 802.11 g standards.
14. The synthesizer of claim 7 wherein the clock signal is a 20 MHz signal and the reference frequencies are obtained by dividing the 20 MHz signal by factors of 3, 6 and 15 to generate reference frequencies of 6.667 MHz, 3.333 MHz and 1.333 MHz, wherein the reference frequencies are based on frequency bands for 802.11a, 802.11b and 802.11 g communication standards.
15. The synthesizer of claim 14 wherein the feedback loop of the PLL does not employ a divide by 2 circuit to divide the VCO signal by a factor of 2 in the feedback loop.
16. A method comprising:
dividing a clock signal to generate a reference signal having one of a plurality of reference frequencies, the reference frequencies to be based on a frequency band selected for a communication protocol or protocols;
utilizing the reference signal to drive a front end of a phase locked loop (PLL) having a feedback loop in which a feedback divider provides an N integer division of an output signal from the PLL in the feedback loop to close loop with the reference signal at a front end of the PLL, in which a value for feedback factor N to be used in the N integer division is to be based on a particular channel frequency selected and in which the feedback factor N is to be selected to provide a highest reference frequency available from the plurality of reference frequencies to generate the reference signal.
17. The method of claim 16 further including utilizing the reference frequencies based on frequency bands for 802.11a, 802.11b and 802.11 g communication standards.
18. The method of claim 17 wherein the clock signal is a 20 MHz signal and the reference frequencies are obtained by dividing the 20 MHz signal by factors of 3, 6 and 15 to generate reference frequencies of 6.667 MHz, 3.333 MHz and 1.333 MHz.