System and method for gate formation in a semiconductor device
View Patent ↗A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to form at least one memory cell stack. The memory device is cleaned to remove the mask. A silicide region is formed within the second layer in the at least one memory cell stack, where the silicide region in each memory cell stack is bounded by the spacers.
1. A method for forming a memory device, comprising:
forming a first layer over a substrate;
forming a second layer over the first layer;
forming a mask over the second layer;
forming spacers adjacent opposite side surfaces of the mask;
etching the second layer to form at least one memory cell stack;
forming a dielectric layer over the memory device;
etching the dielectric layer to expose at least an upper surface of the at least one memory cell stack;
removing the mask; and
forming a silicide region on the second layer in the at least one memory cell stack,
wherein the silicide region in each memory cell stack is bounded by the spacers.
2. The method of claim 1 , further comprising:
forming a second dielectric layer on the substrate; and
forming a charge storage element on the second dielectric layer, where the first layer comprises an oxide layer formed on the charge storage element.
3. The method of claim 1 , wherein the second layer comprises a polysilicon layer.
4. The method of claim 3 , wherein the polysilicon layer has a thickness ranging from about 500 Å to about 2500 Å.
5. The method of claim 1 , wherein the mask is formed of silicon oxide.
6. The method of claim 1 , wherein the mask has a thickness ranging from about 500 Å to about 1500 Å and a width ranging from about 500 Å to about 2000 Å.
7. The method of claim 1 , wherein forming spacers comprises:
depositing a spacer layer over the memory device; and
etching the spacer layer to form the spacers adjacent opposite side surfaces of the mask.
8. The method of claim 1 , wherein the spacers have a substantially rabbit-ear-shaped cross-section on opposite sides of the mask.
9. The method of claim 1 , wherein the spacers are formed of silicon oxide.
10. The method of claim 1 , wherein the spacers have a width ranging from about 100 Å to about 1000 Å.
11. The method of claim 1 , wherein forming the spacers comprises:
depositing a spacer layer by chemical vapor deposition.
12. The method of claim 1 , wherein the dielectric layer comprises a silicon nitride.
13. The method of claim 1 , wherein the forming a silicide region comprises:
depositing a metal on the second layer of the at least one memory cell stack; and
thermally annealing the memory device to create the silicide region on the second layer of the at least one memory cell stack.
14. The method of claim 12 , wherein thermally annealing comprises:
annealing the memory device at a temperature ranging from about 400° C. to about 600° C. to form a metal-silicon compound;
removing unreacted metal from the memory device; and
thermally annealing the memory device at a temperature ranging from about 700° C. to about 900° C. to change the metal-silicon compound to a metal silicide to create the silicide region on the second layer of the at least one memory cell stack.
15. The method of claim 1 , comprising:
removing the spacers.
16. The method of claim 15 , wherein removing the spacers comprises etching the memory device to remove the spacers.
17. The method of claim 1 , comprising:
forming a charge storage layer above the first layer, wherein the first layer is a tunnel oxide layer; and
forming a intergate dielectric layer above the charge storage layer,
wherein the second layer is a control gate layer formed over the intergate dielectric layer.
18. A method for making a semiconductor memory device, comprising:
forming at least one memory cell stack over a substrate, wherein the at least one memory cell stack comprises:
a first dielectric layer formed on the substrate;
a charge storage element formed on the first dielectric layer;
an intergate dielectric formed on the charge storage element; and
a gate layer formed over the intergate dielectric;
forming a mask over the gate layer;
forming spacers over the gate layer on opposite sides of the mask;
forming a dielectric layer over the semiconductor memory device;
etching the dielectric layer to expose at least an upper surface of the mask;
removing the mask; and
forming a silicide region in the gate layer, wherein the silicide region is prevented from extending into the dielectric layer by the spacers.