Control gate profile for flash technology

1. A nonvolatile memory device, comprising:

a substrate;

a first insulating layer over the substrate;

a first semiconductor layer formed over the first insulating layer to provide a floating gate for the nonvolatile memory device;

a second insulating layer over the first semiconductor layer; and

a second semiconductor layer formed over the second insulating layer and above the floating gate to provide a control gate for the nonvolatile memory device, wherein a top width of the floating gate and a bottom width of the control gate substantially match, but a sloped profile of the control gate has a top width that is substantially less than the bottom width.

2. The nonvolatile memory device of claim 1 wherein the width at the top of the control gate ranges from 190 to 200 nms and the width at the bottom ranges from 210 to 220 nanometers (nms).

3. The nonvolatile memory device of claim 1 wherein the sloped profile provides an average width differential of about 20 nanometers (nm) from the top to the bottom of the control gate.

4. The nonvolatile memory device of claim 1 further including:

a drain region in the substrate; and

a contact to the drain region that is spaced apart from the control gate, where a distance from a top edge of the control gate to the contact is greater than a distance from a bottom edge of the control gate to the contact.

5. The nonvolatile memory device of claim 4 wherein the distance from the top edge of the control gate to the contact is about 10 nm greater than the distance from the bottom edge of the control gate to the contact.

6. The nonvolatile memory device of claim 1 wherein the second insulating layer is a stacked film of silicon dioxide-silicon nitride-silicon dioxide (ONO).

7. A flash memory comprising:

a substrate;

a first insulating layer over the substrate;

a first polysilicon layer over the first insulating layer;

a second insulating layer over the first polysilicon layer;

a second polysilicon layer over the second insulating layer and in a plane above the first polysilicon layer that is etched to have a tapered profile where a top width is than a bottom width; and

a drain region formed in the substrate and having a contact region on one side of the first and second polysilicon layers that have substantially matching surfaces adjacent to the second insulating layer.

8. The flash memory of claim 7 wherein the second polysilicon layer is a control gate having a sloped profile where the top surface edge is at least 5 nanometers (nm) further from the contact region than the bottom surface edge.

9. The flash memory of claim 7 wherein the first polysilicon layer is a floating gate having a vertical profile where the top surface edge and the bottom surface edge are substantially a same distance from the contact region.

10. The flash memory of claim 9 wherein a source region and the drain region are formed in the substrate where diffused regions are in alignment with spacers on either side of the first polysilicon layer that forms a floating gate and the second polysilicon layer that forms a control gate.