Patent Assignment
Reel/Frame 064928/0832
Assignment of Assignor's Interest
Recorded: 2023-09-17
Pages: 56
Assignor
INTEL CORPORATION
Executed: 2021-12-29
Assignee
INTEL NDTM US LLC
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(367)
Block-Level Read While Write Method and Apparatus
Patent:
6,772,273 →
Application:
09/608,454 →
Updating a File in a Fragmented File System
Sample and Hold Voltage Reference Source
Method of Tracking Objects for Application Modifications
Space Allocation and Testing for Data in a Nonvolatile Memory
Method and Apparatus for Processing Commands in a Queue Coupled to a System or Memory
Reducing Level Shifter Standby Power Consumption
Patent:
6,385,099 →
Application:
09/811,025 →
Flash Memory Low-Latency Cache
Method and System Using a Virtual Lock for Boot Block Flash
Virtual-Port Memory and Virtual-Porting
Flash Device Operating from a Power-Supply-in-Package (Psip) or from a Power Supply on Chip
Using Multiple Status Bits Per Cell for Handling Power Failures During Write Operations
Patent:
6,549,457 →
Application:
10/077,428 →
Reducing Level Shifter Standby Power Consumption
Storing Data in Non-Volatile Memory Devices
Dual Trench Isolation Using Single Critical Lithographic Patterning
Method and System to Retrieve Information
High Precision Charge Pump Regulation
Patent:
6,642,774 →
Application:
10/187,219 →
Automatic Power Savings Stand-by Control for Non-Volatile Memory
Mitigating Access Penalty of a Semiconductor Nonvolatile Memory
Providing Protection Against Transistor Junction Breakdowns from Supply Voltage
High Precision Charge Pump Regulation
Dynamic Prefetch in Continuous Burst Read Operation
Storing Data in-Non-Volatile Memory Devices
Memory Defect Detection and Self-Repair Technique
Non-Volatile Configuration Data Storage for a Configurable Memory
Utilizing Paging to Support Dynamic Code Updates
Step Voltage Generation
Control Gate Profile for Flash Technology
Dual Mode Negative Voltage Switching
Cascode Protected Negative Voltage Switching
Memory Array with Pseudo Single Bit Memory Cell and Method
Distributed and Packed Metadata Structure for Disk Cache
Secure Booting from a Memory Device
Step Voltage Generator
Scheme for Securing a Memory Subsystem or Stack
Scheme for Securing Locally Generated Data with Authenticated Write Operations
An Apparatus and Method for Testing Removable Flash Memory Devices
Configuring Levels of Program/Erase Protection in Flash Devices
Systems and Techniques for Non-Volatile Memory Buffering
Encoding, Clock Recovery, and Data Bit Sampling System, Apparatus, and Method
Techniques to Truncate Data Files in Nonvolatile Memory
Method, Apparatus and System for Reverting Fat Cluster Number to File Id and Offset of Non-Fat Flash File System
Methods and Apparatus for Providing a Read Access Control System Associated with a Flash Device
Updating a Memory Block Without Status Logging
Accelerating Integrity Checks of Code and Data Stored in Non-Volatile Memory
Header Blocks for Flash Memory Writes
Performance or Power-Optimized Code/Data Storage for Nonvolatile Memories
Detection and Correction of Defects in Semiconductor Memories
Ddr Flash Implementation with Direct Register Access to Legacy Flash Functions
Ddr Flash Implementation with Hybrid Row Buffers and Direct Access Interface to Legacy Flash Functions
Flash Memory Device with Improved Erase Operation
Gate Structures for Flash Memory and Methods of Making Same
Apparatus, System, and Method for Multiple-Segment Floating Gate
Methods, Apparatus, and Systems for Flash Memory Bit Line Charging
Method, Apparatus, and System for Improved Erase Operation in Flash Memory
Selective Bit Line Precharging in Non Volatile Memory
Method, Apparatus, and System for Flash Memory
Apparatus, Method, and System for Flash Memory
Dielectric Barrier for Nanocrystals
Low-Cost Pseudo-Random Nonce Value Generation System and Method
Multi-Level Memory Cell Sensing
Method, System, and Apparatus for Ecc Protection of Small Data Structures
Command-Based Control of Nand Flash Memory
Erase Cycle Counting in Non-Volatile Memories
Use of a Shutdown Object to Improve Initialization Performance
Process, Voltage, and Temperature Compensated Clock Generator
Self-Aligned Charge-Trapping Layers for Non-Volatile Data Storage, Processes of Forming Same, and Devices Containing Same
Hetero-Bimos Injection Process for Non-Volatile Flash Memory
Authenticated Nonvolatile Memory Signing Operations
Multi-Level Cell Serial-Parallel Sense Scheme for Non-Volatile Flash Memory
Program-Verify Sensing for a Multi-Level Cell (Mlc) Flash Memory Device
Method and Apparatus for Flash Memory Reclaim
Method and Circuit for Performing Read Operation in a Nand Flash Memory
Segmented Bit Line for Flash Memory
Arrangements for Operating a Memory Circuit
Continuous Isochronous Read Access and Measurement of Data Stored in Non-Volatile Memory
Voltage Reference Generator Using Big Flash Cell
Methods and Apparatuses for Refreshing Non-Volatile Memory
Insitu Formation of Inverse Floating Gate Poly Structures
Memory Array with Pseudo Single Bit Memory Cell and Method
Device, System, and Method of Bit Line Selection of a Flash Memory
Data Storage and Processing Algorithm for Placement of Multi - Level Flash Cell (Mlc) Vt
Stack Position Location Identification for Memory Stacked Packages
Circuit and Method for Pre-Charging from Both Ends of an Array in a Read Operation in Nand Flash Memory
Divided Bitline Flash Memory Array with Local Sense and Signal Transmission
Vertical Memory Device and Method
Vertical Memory Device and Method
Charge Pump Warm-Up Current Reduction
Systems and Methods for Discrete Channel Decoding of Ldpc Codes for Flash Memory
Systems and Methods to Reduce Interference Between Memory Cells
Methods and Arrangements to Remap Non-Volatile Storage
Vcc Control Inside Data Register of Memory Device
Methods and Apparatuses for Programming Flash Memory Using Modulated Pulses
Seed Layer for Reduced Resistance Tungsten Film
Floating Gate Structures
Program Acceleration of a Memory Device
Voltage Reference Generator for Flash Memory
Current Sensing Scheme for Non-Volatile Memory
Method, Apparatus and System for Reverting Fat Cluster Number to File Id and Offset of Non-Fat Flash File System
Boosting Seed Voltage for a Memory Device
Apparatus and Methods for Improved Flash Cell Characteristics
Etch Stop Structures for Floating Gate Devices
Isolated P-Well Architecture for a Memory Device
Dynamic Wordline Start Voltage for Nand Programming
Memory Device and Memory Interface
Initiative Wear Leveling for Non-Volatile Memory
Method and System to Improve the Performance of a Multi-Level Cell (Mlc) Nand Flash Memory
Systems and Techniques for Non-Volatile Memory Buffering
Source Bias Shift for Multilevel Memories
Method of Fabricating a Semiconductor Device Having Gate Finger Elements Extended Over a Plurality of Isolation Regions Formed in the Source and Drain Regions
Repurposing Nand Ready/Busy Pin as Completion Interrupt
Flash Memory and Associated Methods
Nand Programming Technique
Pitch Division Patterning Techniques
Multi-Cell Vertical Memory Nodes
Nand Memory Programming Method Using Double Vinhibit Ramp for Improved Program Disturb
Technique to Reduce Fg-Fg Interference in Multi Bit Nand Flash Memory in Case of Adjacent Pages Not Fully Programmed
Depletion Mode Circuit Protection Device
Arrangement of Pairs of Nand Strings That Share Bitline Contacts While Utilizing Distinct Sources Lines
Method and System to Isolate Memory Modules in a Solid State Drive
Vcc Control Inside Data Register of Memory Device
Charge Equilibrium Acceleration in a Floating Gate Memory Device via a Reverse Field Pulse
Method and Apparatus for Improving Endurance of Flash Memories
Non-Volatile Storage Element Having Dual Work-Function Electrodes
Contact Integration for Three-Dimensional Stacking Semiconductor Devices
Memory Cell Using Bti Effects in High-K Metal Gate Mos
Method and Apparatus for Addressing Memory Arrays
Non-Volatile Memory Error Mitigation
Techniques to Truncate Data Files in Nonvolatile Memory
Nibble Encoding for Improved Reliability of Non-Volatile Memory
Vertical Nand Memory
Extended Select Gate Lifetime
Three Dimensional Nand Flash with Self-Aligned Select Gate
Method of Fabricating a Semiconductor Device Including a Gate Having a Plurality of Fingers Extended Over a Plurality of Isolation Regions
Self-Disabling Chip Enable Input
Compensating for Off-Current in a Memory
Using a Reference Bit Line in a Memory
Column Address Decoding
Nand Memory Management
Techniques to Store Configuration Information in an Option Read-Only Memory
Error Corrected Pre-Read for Upper Page Write in a Multi-Level Cell Memory
Self-Aligned Floating Gate in a Vertical Memory Structure
Lower Page Read for Multi-Level Cell Memory
Erase and Soft Program for Vertical Nand Flash
Sharing Serial Peripheral Interface Flash Memory in a Multi-Node Server System on Chip Platform Environment
Three Dimensional Memory Structure
Local Buried Channel Dielectric for Vertical Nand Performance Enhancement and Vertical Scaling
Tungsten Salicide Gate Source for Vertical Nand String to Control on Current and Cell Pillar Fabrication
Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory Device to Reduce Peak Power Consumption
Programmable/Re-Programmable Device in High-K Metal Gate Mos
Multi-Pulse Programming for Memory
Antifuse Element Utilizing Non-Planar Topology
Adaptive Moving Read References for Memory Cells
Method and System to Obtain State Confidence Data Using Multistrobe Read of a Non-Volatile Memory
Method and Apparatus for Treatment of State Confidence Data Retrieved from a Non-Volatile Memory Array
Maximum-Likelihood Decoder in a Memory Controller for Synchronization
Nand Memory Array with Mismatched Cell and Bitline Pitch
Use of Etch Process Post Wordline Definition to Improve Data Retention in a Flash Memory Device
Three Dimensional Memory Control Circuitry
Charge Pump Redundancy in a Memory
Chunk Redundancy Architecture for Memory
Self-Disabling Chip Enable Input
Repurposing Nand Ready/Busy Pin as Completion Interrupt
Independently Selective Tile Group Access with Data Structuring
Data Storage and Variable Length Error Correction Information
Metal Floating Gate Composite 3D Nand Memory Devices and Associated Methods
Program Vt Spread Folding for Nand Flash Memory Programming
Memory Structure with Self-Aligned Floating and Control Gates and Associated Methods
Stacked Thin Channels for Boost and Leakage Improvement
Methods of Tunnel Oxide Layer Formation in 3D Nand Memory Structures and Associated Devices
Ramping Inhibit Voltage During Memory Programming
Building Stacked Hollow Channels for a Three Dimensional Circuit Device
Error Correcting (Ecc) Memory Compatibility
Boot Management in a Non-Volatile Memory System
Self-Aligned Charge-Trapping Layers for Non-Volatile Data Storage, Processes of Forming Same, and Devices Containing Same
Through Array Routing for Non-Volatile Memory
Application:
14/310,391 →
Publication:
US 2015/0371925
Extended Select Gate Lifetime
Nand Memory Devices Systems, and Methods Using Pre-Read Error Recovery Protocols of Upper and Lower Pages
Aluminum Oxide Landing Layer for Conductive Channels for a Three Dimensional Circuit Device
Appointing Semiconductor Dice to Enable High Stacking Capability
Application:
14/483,260 →
Publication:
US 2016/0078939
Selectable Memory Access Time
Sensing with Boost
Nand Memory Addressing
Source-Channel Interaction in 3D Circuit
Capping Poly Channel Pillars in Stacked Circuits
Patent:
9,263,459 →
Application:
14/498,673 →
Techniques for Adaptive Moving Read References for Memory Cell Read Error Recovery
Compensating for Off-Current in a Memory
Self-Aligned Floating Gate in a Vertical Memory Structure
Using Counters and a Table to Protect Data in a Storage Device
Apparatus and Method for Mitigating Loss of Signal Content
Double Data Rate in Parallel Testing
Patent:
9,293,224 →
Application:
14/569,983 →
Refresh Logic to Refresh Only Memory Cells Having a First Value
Voltage Ramping Detection
Tier Mode for Access Operations to 3D Memory
Tungsten Salicide Gate Source for Vertical Nand String to Control on Current and Cell Pillar Fabrication
Current Leakage Reduction in 3D Nand Memory
Patent:
9,424,936 →
Application:
14/666,147 →
Pillar Arrangement in Nand Memory
Extended Select Gate Lifetime
Memory Cell Having Isolated Charge Sites and Method of Fabricating Same
Three Dimensional Memory Structure
Method and Apparatus for Defect Management in a Non-Volatile Memory Device
Provision of Etch Stop for Wordlines in a Memory Device
Patent:
9,520,402 →
Application:
14/835,648 →
Self-Aligned Floating Gate in a Vertical Memory Structure
Power Loss Capacitor Test Using Voltage Ripple
Methods and Apparatus to Program Multi-Level Cell Memory Using Target-Only Verify
Patent:
9,478,305 →
Application:
14/851,479 →
Multiple Blocks Per String in 3D Nand Memory
Three Dimensional Memory Device Having Isolated Periphery Contacts Through an Active Layer Exhume Process
On Demand Knockout of Coarse Sensing Based on Dynamic Source Bounce Detection
Antifuse Element Utilizing Non-Planar Topology
Local Buried Channel Dielectric for Vertical Nand Performance Enhancement and Vertical Scaling
Segmented Erase in Memory
Three Dimensional Memory Control Circuitry
Nand Memory Array with Mismatched Cell and Bitline Pitch
Stacked Thin Channels for Boost and Leakage Improvement
Methods and Apparatus to Read Memory Cells Based on Clock Pulse Counts
Patent:
9,530,513 →
Application:
14/952,322 →
Lower Page Read for Multi-Level Cell Memory
Reducing Verification Checks When Programming a Memory Device
Memory Devices and Systems Having Reduced Bit Line to Drain Select Gate Shorting and Associated Methods
Capping Poly Channel Pillars in Stacked Circuits
Predictive count fail byte (CFBYTE) for non-volatile memory
Vertical memory having varying storage cell design through the storage cell stack
Erase and Soft Program for Vertical Nand Flash
Slit Stress Modulation in Semiconductor Substrates
Three Dimensional Storage Cell Array with Highly Dense and Scalable Word Line Design Approach
Methods and Apparatus to Perform Erase-Suspend Operations in Memory Devices
N Plane to 2N Plane Interface in a Solid State Drive (Ssd) Architecture
High Voltage Tolerant Word-Line Driver
Three Dimensional Nand Flash with Self-Aligned Select Gate
Ramping Inhibit Voltage During Memory Programming
Method and Apparatus for Reducing Data Program Completion Overhead in Nand Flash
Method and Apparatus for Improving Sequential Reading in Nand Flash
Self-Aligned Floating Gate in a Vertical Memory Structure
Pillar Arrangement in Nand Memory
Three Dimensional Memory Device with Access Signal Triggering from Voltage Pump Output Levels
Method and Apparatus for Protecting Lower Page Data During Programming in Nand Flash
Patent:
9,703,494 →
Application:
15/276,080 →
Method and Apparatus for Initiating Pre-Read Operation Before Completion of Data Load Operation
Patent:
9,823,880 →
Application:
15/281,439 →
Method and Apparatus for Avoiding Bus Contention After Initialization Failure
Solid State Memory Component
Patent:
9,857,989 →
Application:
15/283,296 →
Electronic Component Guard Ring
Methods and Apparatus to Program Multi-Level Cell Memory Using Target-Only Verify
Methods and Apparatus to Read Memory Cells Based on Clock Pulse Counts
Nand Memory Addressing
Achieving Consistent Read Times in Multi-Level Non-Volatile Memory
Patent:
9,811,269 →
Application:
15/395,062 →
Performing Read Operations on a Memory Device
Patent:
9,865,357 →
Application:
15/395,700 →
A Solid State Memory Device, and Manufacturing Method Thereof
Aluminum Oxide Landing Layer for Conductive Channels for a Three Dimensional Circuit Device
Method and Apparatus for Treatment of State Confidence Data Retrieved from a Non-Volatile Memory Array
Reducing Verification Checks When Programming a Memory Device
Method and Apparatus for Process Corner Compensation for Memory State Sensing
Method and Apparatus for Shielded Read to Reduce Parasitic Capacitive Coupling
Write Process for a Non Volatile Memory Device
Flash Memory Cells, Components, and Methods
Programming Memory Devices
Conductive Channels and Source Line Coupling
Methods and Apparatus to Read Memory Cells Based on Clock Pulse Counts
Nand Memory Array with Mismatched Cell and Bitline Pitch
Method and Apparatus for Reducing Capacitance of Input/Output Pins of Memory Device
Method and Apparatus for Improved Etch Stop Layer or Hard Mask Layer of a Memory Device
Chunk Redundancy Architecture for Memory
Selective Body Reset Operation for Three Dimensional (3D) Nand Memory
Read and Program Operations in a Memory Device
Computer Memory
Memory Devices and Systems Having Reduced Bit Line to Drain Select Gate Shorting and Associated Methods
Ramping Inhibit Voltage During Memory Programming
Method and Apparatus for Dynamically Determining Start Program Voltages for a Memory Device
Patent:
10,224,107 →
Application:
15/720,984 →
3D Nand with Integral Drain-End Select Gate (Sgd)
Method and Apparatus for Specifying Read Voltage Offsets for a Read Command
Concurrent Copying of First and Second Subsets of Pages from Media Such as Slc Nand to Media Such as Qlc or Mlc Nand for Completion of Copying of Data
Polysilicon Doping Controlled 3D Nand Etching
Patent:
10,096,610 →
Application:
15/721,544 →
Method and Apparatus for Per-Deck Erase Verify and Dynamic Inhibit in 3D Nand
Flash Memory Devices Incorporating a Polydielectric Layer
Sense Matching for Hard and Soft Memory Reads
Patent:
10,163,500 →
Application:
15/721,774 →
Multiple Blocks Per String in 3D Nand Memory
Methods of Tunnel Oxide Layer Formation in 3D Nand Memory Structures and Associated Devices
Application:
15/798,352 →
Publication:
US 2018/0294272
Achieving Consistent Read Times in Multi-Level Non-Volatile Memory
Wordline Bridge in a 3D Memory Array
Method and System for Reducing Program Disturb Degradation in Flash Memory
Block by Deck Operations for Nand Memory
Data Storage Device with Operation Based on Temperature Difference
Background Data Refresh Using a System Timestamp in Storage Devices
Data Path Training and Timing Signal Compensation for Non-Volatile Memory Device Interface
System and Method for Performing a Concurrent Multiple Page Read of a Memory Array
Prefix Opcode Method for Slc Entry with Auto-Exit Option
Application:
15/845,596 →
Publication:
US 2019/0042130
Method and System for Compensating for Floating Gate-to-Floating Gate (Fg-Fg) Interference in Flash Memory Cell Read Operations
Cache Utility Modeling for Automated Cache Configuration
Internal Copy to Handle Nand Program Fail
Mass Storage Device Capable of Fine Grained Read and/or Write Operations
Application:
15/857,406 →
Publication:
US 2019/0042153
Stream Classification Based on Logical Regions
Solid State Memory Component
Memory Block Access Modes for a Storage Device
Flash Memory Cells
Slit Stress Modulation in Semiconductor Substrates
Ordering of Memory Device Mapping to Reduce Contention
Memory-Addressed Maps for Persistent Storage Device
Non-Volatile Memory Cloning with Hardware Copy-on-Write Support
Power-Down/Power-Loss Memory Controller
Flash Memory Components and Methods
Memory Device with Reduced Capacitance
Modified Floating Gate and Dielectric Layer Geometry in 3D Memory Arrays
Three Dimensional Storage Cell Array with Highly Dense and Scalable Word Line Design Approach
Failure Indicator Predictor (Fip)
Memory Device with Vertical String Drivers
Cache Utilization of Backing Storage for Aggregate Bandwidth
Program Verification Time Reduction in Non-Volatile Memory Devices
Three Dimensional Memory Device Having Isolated Periphery Contacts Through an Active Layer Exhume Process
Application:
16/153,422 →
Publication:
US 2019/0051662
Techniques for Providing Signal Calibration Data
Memory Device with a Split Staircase
Application:
16/184,641 →
Publication:
US 2020/0152650
Channel Conductivity in Memory Structures
Duty Cycle Control Circuitry for Input/Output (I/O) Margin Control
Solid State Drive with Reduced Host Oversight of High Priority Read Command
Application:
16/264,390 →
Publication:
US 2019/0163403
Memory Programming Techniques
Methods and Apparatus to Perform Erase-Suspend Operations in Memory Devices
Host Defined Bandwidth Allocation for Ssd Tasks
Program Suspend-Resume Techniques in Non-Volatile Storage
Method and Apparatus for Dynamically Determining Start Program Voltages for a Memory Device
3D Nand Structures Including Group Iii-N Material Channels
Storage System with Reconfigurable Number of Bits Per Cell
Application:
16/370,743 →
Publication:
US 2019/0227751
Achieving Consistent Read Times in Multi-Level Non-Volatile Memory
Apparatus, Systems, and Methods to Reclaim Storage Associated with Cached Data
Method, System, and Apparatus for Multi-Tiered Progressive Memory Program Operation Suspend and Resume
Program Verify Technique for Non-Volatile Memory
Erase and Soft Program for Vertical Nand Flash
Method for Making a Flash Memory Device
Compressing Error Vectors for Decoding Logic to Store Compressed in a Decoder Memory Used by the Decoding Logic
Floating Block Select Based Programming Time (Tprog)
Patent:
10,783,941 →
Application:
16/423,916 →
Solid State Memory Component
Memory Arrays with Bonded and Shared Logic Circuitry
3-Dimensional Flash Memory with Increased Floating Gate Length
Patent:
10,784,274 →
Application:
16/441,500 →
Non-Volatile Memory with Storage Nodes Having a Radius of Curvature
Patent:
10,825,831 →
Application:
16/457,694 →
Flash Data Compression Decompression Method and Apparatus
Dynamic Single Level Cell Memory Controller
Defective Bit Line Management in Connection with a Memory Access
Permutation of Bit Locations to Reduce Recurrence of Bit Error Patterns in a Memory Device
Reducing Power Consumption in Nonvolatile Memory Due to Standby Leakage Current
Ssd Having a Parallelized, Multi-Level Program Voltage Verification
System and Method for Performing a Concurrent Multiple Page Read of a Memory Array
Application:
16/593,868 →
Publication:
US 2020/0090743
Integrated Word Line Contact Structures in Three-Dimensional (3D) Memory Array
Application:
16/681,164 →
Publication:
US 2021/0143100
Detection and Error-Handling of High Error Rate Blocks During Copyback
Electronic Component Guard Ring
System Approach to Reduce Stable Threshold Voltage (Vt) Read Disturb Degradation
Techniques for Preventing Read Disturb in Nand Memory
Read Quality of Service for Non-Volatile Memory
Method and Apparatus for Performing an Erase Operation Comprising a Sequence of Micro-Pulses in a Memory Device
Apparatuses, Systems, and Methods for Heating a Memory Device
Using Variable Voltages to Discharge Electrons from a Memory Array During Verify Recovery Operations
Boosted Bitlines for Storage Cell Programmed State Verification in a Memory Array
Patent:
11,056,203 →
Application:
16/788,194 →
Device, System, and Method to Verify Data Programming of a Multi-Level Cell Memory Based on One of Temperature, Pressure, Wear Condition or Relative Position of the Memory Cell
Resistance Reduction for Word Lines in Memory Arrays
Non Volatile Flash Memory with Improved Verification Recovery and Column Seeding
Configurable Nvm Set to Tradeoff Between Performance and User Space
Flash Memory Chip That Modulates Its Program Step Voltage as a Function of Chip Temperature
Vertical String Driver with Channel Field Management Structure
Vertical String Driver with Extended Gate Junction Structure
Method and System for Reducing Program Disturb Degradation in Flash Memory
Smart Prologue for Nonvolatile Memory Program Operation
Disaggregated Rack Mount Storage Side Transaction Support
Method and Apparatus to Mitigate Hot Electron Read Disturbs in 3D Nand Devices
Automatic Read Calibration Operations
Method of Detecting Read Hotness and Degree of Randomness in Solid-State Drives (Ssds)
Flash Memory Having Improved Performance as a Consequence of Program Direction Along a Flash Storage Cell Column
Application:
17/023,094 →
Publication:
US 2022/0084606
Asymmetric Junctions of High Voltage Transistor in Nand Flash Memory
Techniques to Improve Error Correction Using an Xor Rebuild Scheme of Multiple Codewords and Prevent Miscorrection from Read Reference Voltage Shifts
String Current Reduction During Multistrobe Sensing to Reduce Read Disturb
Progressive Program Suspend Resume
Variable Error Correction Codeword Packing to Support Bit Error Rate Targets
Defective Bit Line Management in Connection with a Memory Access
Reduced-Pass Erase Verify for Nonvolatile Storage Media
Application:
17/253,095 →
Publication:
US 2021/0272638