Encoding, clock recovery, and data bit sampling system, apparatus, and method
View Patent ↗A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period. An apparatus, system, and method to embed a sampling clock signal via an encoded signal comprising n bits and to transmit the encoded signal to a single-wire as a serial bit sequence of n bits. The encoded signal represents a logic bit having an encoding clock period T CLK . Other embodiments are described and claimed.
1. An apparatus, comprising:
a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input, said first clock input to receive an encoded signal from a single-wire, said encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit, said pulsed digital module to capture an edge of said encoded signal at said first clock input in accordance with a logic level coupled to said first data input; and
a delay module comprising a delay input coupled to said data output and a delay output coupled to said reset input, said delay module to delay said captured edge by a predetermined period and to generate a delay signal from said delay output after said predetermined period;
wherein said pulsed digital module is to generate a first clock edge of said sampling clock at said data output after said predetermined period.
2. The apparatus of claim 1 , comprising:
a shift register comprising a second clock input coupled to said data output and a second data input to receive said encoded signal, said shift register to sample said encoded signal at said first clock edge of said sampling clock.
3. The apparatus of claim 1 , wherein said pulsed digital module to capture a rising edge at said first clock input in accordance with a high logic level coupled to said first data input.
4. The apparatus of claim 1 , wherein said pulsed digital module to capture a falling edge at said first clock input in accordance with a low logic level coupled to said first data input.
5. The apparatus of claim 1 , wherein said encoded signal is encoded with an encoding clock period T CLK and a sampling window period T sw is defined as:
T SW =±[( n -2)/2] T CLK ;
wherein said encoded signal comprises n bits.
6. A system, comprising:
a flash memory coupled to a single-wire serial link; and
a pulsed digital module coupled to said single-wire serial link, said pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input, said first clock input to receive an encoded signal from said single-wire serial link, said encoded signal comprising a serial bit sequence comprising a clock signal embedded data bit, said pulsed digital module to capture an edge of said encoded signal at said first clock input in accordance with a logic level coupled to said first data input; and
a delay module comprising a delay input coupled to said data output and a delay output coupled to said reset input, said delay module to delay said captured edge by a predetermined period and to generate a delay signal from said delay output after said predetermined period;
wherein said pulsed digital module is to generate a first clock edge of said sampling clock at said data output after said predetermined period.
7. The system of claim 6 , comprising:
a shift register comprising a second clock input coupled to said data output and a second data input to receive said encoded signal, said shift register to sample said encoded signal at said first clock edge of said sampling clock.
8. The system of claim 6 , wherein said pulsed digital module to capture a rising edge at said first clock input in accordance with a high logic level coupled to said first data input.
9. The system of claim 6 , wherein said pulsed digital module to capture a falling edge at said first clock input in accordance with a low logic level coupled to said first data input.
10. The system of claim 6 , wherein said encoded signal is encoded with an encoding clock period T CLK and a sampling window period T sw is defined as:
T SW =±[( n -2)/2] T CLK ;
wherein said encoded signal comprises n bits.
11. A method, comprising:
embedding a sampling clock signal via an encoded signal comprising n bits, said encoded signal represents a logic bit having an encoding clock period T CLK ;
transmitting said encoded signal to a single-wire as a serial bit sequence of n bits;
encoding an edge after each n bit of said serial single-wire bit sequence of n bits.
12. The method of claim 11 , comprising:
representing said encoded signal is a pulse of a predetermined width;
wherein a leading bit or a trailing bit of said n bits comprising said encoded signal is logically inverted relative to the remaining n-1 bits.
13. The method of claim 11 , wherein said encoding an edge comprises:
encoding a rising edge after each n bit of said serial single-wire bit sequence of n bits.
14. The method of claim 11 , wherein said encoding an edge comprises:
encoding a falling edge after each n bit of said serial single-wire bit sequence of n bits.
15. The method of claim 11 , comprising:
encoding said encoded signal to be decoded by a sampling window period T SW determined by the relationship T sw =±[(n-2)/2]T CLK .
16. An apparatus, comprising:
an encoder to embed a sampling clock signal via an encoded signal comprising n bits, said encoded signal represents a logic bit having an encoding clock period T CLK ; and
to transmit said encoded signal to a single-wire as a serial bit sequence of n bits, wherein said encoder is to encode an edge after each n bit of said serial single-wire bit sequence of n bits.
17. The apparatus of claim 16 , wherein said encoder is to represent said encoded signal as a pulse of a predetermined width, wherein a leading bit or a trailing bit of said n bits comprising said encoded signal is logically inverted relative to the remaining n-1 bits.
18. The apparatus of claim 16 , wherein said edge is a rising edge.
19. The apparatus of claim 16 , wherein said edge is a falling edge.
20. The apparatus of claim 16 , wherein said encoder is to encode said encoded signal to be decoded by a sampling window period T sw determined by the relationship T sw =±[(n-2)/2]T CLK .
21. An article comprising a machine-readable storage medium containing instructions that if executed enable a system to embed a sampling clock signal via an encoded signal comprising n bits, said encoded signal represents a logic bit having an encoding clock period T CLK ; encode an edge after each n bit of said serial single-wire bit sequence of n bits; and transmit said encoded signal to a single-wire as a serial bit sequence of n bits.
22. The article of claim 21 , further comprising instructions that if executed enable the system to represent said encoded signal as a pulse of a predetermined width; and to logically invert a leading bit or a trailing bit of said n bits comprising said encoded signal relative to the remaining n-1 bits.
23. The article of claim 21 , wherein the edge is a rising edge.
24. The article of claim 21 , wherein the edge is a falling edge.
25. The article of claim 21 , further comprising instructions that if executed enable the system to encode said encoded signal to be decoded by a sampling window period T sw determined by the relationship T sw =±[(n-2)/2]T CLK .