Method and apparatus for addressing memory arrays

1. A method of addressing a memory system, comprising:

providing a memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module;

optionally, driving the single chip enable signal, enable in/out signals between adjacent memory modules, and a final enable in/out signal from the memory array to a first voltage;

driving an incoming enable in/out signal into the memory array to a second voltage to select a first memory module in the daisy chain;

resetting the selected memory module;

receiving configuration information for the selected memory module by the host controller;

appointing a volume address to the selected memory module to address memory units within the memory module;

setting an outgoing enable in/out signal for the selected memory module to the second voltage;

determining whether another unaddressed memory module exists in the memory array;

selecting the next memory module in the daisy chain when another unaddressed memory module exists; and

repeating resetting the selected memory module, receiving configuration information for the selected memory module by the host controller, appointing a volume address to the selected memory module, setting an outgoing enable in/out signal for the selected memory module to the second voltage, and determining whether another memory module exists in the memory array, when another memory module exists.

2. The method of claim 1 , wherein appointing a volume address to the selected memory module comprises appointing a sequential volume address to the selected memory module.

3. The method of claim 1 , wherein appointing a volume address to the selected memory module comprises appointing a non-sequential volume address to the selected memory module.

4. The method of claim 1 , wherein appointing a volume address to the selected memory module comprises appointing a randomized volume address to the selected memory module.

5. The method of claim 1 , wherein providing a memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module comprises providing a memory system comprising at least one memory array having a plurality of memory modules coupled in a daisy chain with a plurality of enable in/out signals, and a single chip enable signal from a host controller coupled in parallel to each memory module.

6. The method of claim 1 , further including determining whether another determining whether another memory array exists in the memory system after no further memory modules are detected;

selecting an unaddressed memory array when another memory module is not detected; and

repeating optionally driving the single chip enable signal, enable in/out signals between adjacent memory modules, and a final enable in/out signal from the memory array to the first voltage, driving an incoming enable in/out signal into the memory array to the second voltage to select a first memory module in the daisy chain, resetting the selected memory module, receiving configuration information for the selected memory module by the host controller, appointing a volume address to the selected memory module, setting an outgoing enable in/out signal for the selected memory module to the second voltage, and determining whether another memory module exists in the memory array, when another memory module exists, and determining whether another unaddressed memory array exists in the memory system when no further unaddressed memory modules are detected.

7. The method of claim 6 , further including completing an initialization process when no further unaddressed memory arrays are detected.